 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| S3C94A5/F94A5 8-BIT CMOS MICROCONTROLLER USER'S MANUAL Revision 1.1 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others. Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. S3C94A5/F94A5 8-Bit CMOS Microcontroller User's Manual, Revision 1.1 Publication Number: 21.1-S3-C94A5/F94A5-072005 (c) 2005 Samsung Electronics All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics. Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur. Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product. Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900 TEL: (82)-(031)-209-1934 FAX: (82) (331) 209-1889 Home-Page URL: Http://www.samsungsemi.com/ Printed in the Republic of Korea NOTIFICATION OF REVISIONS ORIGINATOR: PRODUCT NAME: DOCUMENT NAME: DOCUMENT NUMBER: EFFECTIVE DATE: SUMMARY: Samsung Electronics, LSI Development Group, Ki-Heung, South Korea S3C94A5/F94A5 8-bit CMOS Microcontroller S3C94A5/F94A5 User's Manual, Revision 1.1 21.1-S3-C94A5/F94A5-072005 July, 2005 As a result of additional product testing and evaluation, some specifications published in the S3C94A5/F94A5 User's Manual, Revision 1, have been changed. These changes for S3C94A5/F94A5 microcontroller, which are described in detail in the Revision Descriptions section below, are related to the followings: -- Chapter 17. Electrical Data DIRECTIONS: Please note the changes in your copy (copies) of the S3C94A5/F94A5 User's Manual, Revision 1. Or, simply attach the Revision Descriptions of the next page to S3C94A5/F94A5 User's Manual, Revision 1. REVISION HISTORY Revision 0 1 1.1 Date July, 2004 February, 2005 July, 2005 Remark Preliminary spec for internal release only. First edition. Reviewed by Finechips. Second edition. Reviewed by Finechips. REVISION DESCRIPTIONS 1. ELECTRICAL DATA Table 17-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VI VO IOH Ports 1-5 - One I/O pin active All I/O pins active 42-SDIP 44-QFP Output current Low IOL One I/O pin active All I/O pin active 42-SDIP 44-QFP Operating temperature Storage temperature TA TSTG - - - 25 to + 85 - 65 to + 150 + 30 + 100 + 150 C C Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 60 - 90 Unit V V V mA mA Table 17-9. External RC Oscillation (Mode 2) Characteristics (TA = - 25 C to + 85 C, VDD = 2.7 V to 5.5 V) Parameter RC oscillator frequency range (1) Accuracy of RC oscillation (2) Symbol fERC ACCERC Conditions TA = 25 C VDD = 3.3 V, TA = 25 C VDD = 3.3 V, TA = -25 C to 85 C Min 4 -7 -15 Typ - - - Max 8 +7 +15 Unit MHz % RC oscillator setup time (3) tSUERC TA = 25 C - - 10 ms NOTES: 1. The frequency is adjusted by external resistor. 2. The min/max frequencies are within the range of RC OSC frequency (4 MHz to 8 MHz). 3. Data based on characterization results, not tested in production. 4. The external resistor is connected between VDD and XIN pin (XOUT pin should be open). Preface The S3C94A5/F94A5 Microcontroller User's Manual is designed for application designers and programmers who are using the S3C94A5/F94A5 microcontroller for application development. It is organized in two parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters: Chapter 1 Chapter 2 Chapter 3 Product Overview Address Spaces Addressing Modes Chapter 4 Chapter 5 Chapter 6 Control Registers Interrupt Structure SAM88RCRI Instruction Set Chapter 1, "Product Overview," is a high-level introduction to the S3C94A5/F94A5 with a general product description, and detailed information about individual pin characteristics and pin circuit types. Chapter 2, "Address Spaces," explains the S3C94A5/F94A5 program and data memory, internal register file, and mapped control registers, and explains how to address them. Chapter 2 also describes working register addressing, as well as system and user-defined stack operations. Chapter 3, "Addressing Modes," contains detailed descriptions of the six addressing modes that are supported by the CPU. Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. Chapter 5, "Interrupt Structure," describes the S3C94A5/F94A5 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part II. Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for all S3C9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program. A basic familiarity with the information in part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the SAM88RCRI product family and are reading this manual for the first time, we recommend that you first read chapters 1-3 carefully. Then, briefly look over the detailed information in chapters 4, 5, and 6. Later, you can reference the information in part I as necessary. Part II contains detailed information about the peripheral components of the S3C94A5/F94A5 microcontrollers. Also included in part II are electrical, mechanical, MTP, and development tools data. It has 14 chapters: Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Clock Circuit RESET and Power-Down I/O Ports Basic Timer 16-bit Timer 0 16-bit Timer 1 8-bit Timer 2 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Chapter 19 Chapter 20 Watch Timer 10-Bit Analog-To-Digital Converter Serial I/O Interface Electrical Data Mechanical Data S3F94A5 Flash MCU Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C94A5/F94A5 microcontroller: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative. S3C94A5/F94A5 MICROCONTROLLER iii Table of Contents Part I -- Programming Model Chapter 1 Product Overview SAM88RCRI Product Family ................................................................................................................1-1 S3C94A5/F94A5 Microcontroller ...........................................................................................................1-1 Flash..................................................................................................................................................1-1 Features .............................................................................................................................................1-2 Block Diagram ....................................................................................................................................1-3 Pin Assignments.................................................................................................................................1-4 Pin Descriptions ..................................................................................................................................1-6 Pin Circuit Diagrams............................................................................................................................1-8 Chapter 2 Address Spaces Overview .............................................................................................................................................2-1 Program Memory (ROM) ......................................................................................................................2-2 Smart Option ......................................................................................................................................2-3 Register Architecture ...........................................................................................................................2-5 Common Working Register Area (C0H-CFH) .........................................................................................2-6 System Stack.....................................................................................................................................2-7 Chapter 3 Addressing Modes Overview .............................................................................................................................................3-1 Register Addressing Mode (R) ..............................................................................................................3-2 Indirect Register Addressing Mode (IR)..................................................................................................3-3 Indexed Addressing Mode (X) ...............................................................................................................3-7 Direct Address Mode (DA)....................................................................................................................3-10 Relative Address Mode (RA).................................................................................................................3-12 Immediate Mode (IM) ...........................................................................................................................3-12 S3C94A5/F94A5 MICROCONTROLLER v Table of Contents (Continued) Chapter 4 Control Registers Overview .............................................................................................................................................4-1 Chapter 5 Interrupt Structure Overview .............................................................................................................................................5-1 Interrupt Processing Control Points ...............................................................................................5-1 Enable/Disable Interrupt Instructions (EI, DI) ..................................................................................5-1 Interrupt Pending Function Types ..................................................................................................5-2 Interrupt Priority...........................................................................................................................5-2 Interrupt Source Service Sequence................................................................................................5-3 Interrupt Service Routines.............................................................................................................5-3 Generating Interrupt Vector Addresses ..........................................................................................5-3 S3C94A5/F94A5 Interrupt Structure ..............................................................................................5-4 Chapter 6 SAM88RCRI Instruction Set Overview .............................................................................................................................................6-1 Register Addressing ....................................................................................................................6-1 Addressing Modes.......................................................................................................................6-1 Flags Register (FLAGS)...............................................................................................................6-4 Flag Descriptions ........................................................................................................................6-4 Instruction Set Notation................................................................................................................6-5 Condition Codes ..........................................................................................................................6-9 Instruction Descriptions................................................................................................................6-10 vi S3C94A5/F94A5 MICROCONTROLLER Table of Contents (Continued) Part II -- Hardware Descriptions Chapter 7 Clock Circuit Overview .............................................................................................................................................7-1 System Clock Circuit...................................................................................................................7-1 CPU Clock Notation.....................................................................................................................7-1 Main Oscillator Circuits................................................................................................................7-2 Clock Status During Power-Down Modes .......................................................................................7-3 System Clock Control Register (CLKCON).....................................................................................7-4 Stop Control Register (STPCON) ..................................................................................................7-5 Chapter 8 RESET and Power-Down System Reset .....................................................................................................................................8-1 Overview .....................................................................................................................................8-1 Power-Down Modes .............................................................................................................................8-2 Stop Mode..................................................................................................................................8-2 Idle Mode....................................................................................................................................8-3 Hardware Reset Values................................................................................................................8-4 Chapter 9 I/O Ports Overview .............................................................................................................................................9-1 Port Data Registers .....................................................................................................................9-2 Port 1.........................................................................................................................................9-3 Port 2.........................................................................................................................................9-7 Port 3.........................................................................................................................................9-9 Port 4.........................................................................................................................................9-15 Port 5.........................................................................................................................................9-19 Chapter 10 Basic Timer Overview .............................................................................................................................................10-1 Basic Timer Control Register (BTCON) ..........................................................................................10-2 Basic Timer Function Description..................................................................................................10-3 S3C94A5/F94A5 MICROCONTROLLER vii Table of Contents (Continued) Chapter 11 16-bit Timer 0 Overview .............................................................................................................................................11-1 Timer/Counter 0 Control Register (T0CON).....................................................................................11-1 Timer 0 Function Description ........................................................................................................11-4 Chapter 12 16-bit Timer 1 Overview .............................................................................................................................................12-1 Timer/Counter 1 Control Register (T1CON).....................................................................................12-1 Timer 1 Function Description ........................................................................................................12-4 Chapter 13 8-bit Timer 2 Overview .............................................................................................................................................13-1 Timer/Counter 2 Control Register (T2CON).....................................................................................13-1 Timer 2 Function Description ........................................................................................................13-4 Chapter 14 Watch Timer Overview .............................................................................................................................................14-1 Watch Timer Control Register (WTCON)........................................................................................14-2 Watch Timer Circuit Diagram........................................................................................................14-3 Chapter 15 10-Bit Analog-To-Digital Converter Overview .............................................................................................................................................15-1 Function Description............................................................................................................................15-1 Conversion Timing .......................................................................................................................15-2 A/D Converter Control Register (ADCON).......................................................................................15-2 Internal Reference Voltage Levels..................................................................................................15-3 Block Diagram ....................................................................................................................................15-4 viii S3C94A5/F94A5 MICROCONTROLLER Table of Contents (Continued) Chapter 16 Serial I/O Interface Overview .............................................................................................................................................16-1 Programming Procedure...............................................................................................................16-1 SIO Control Registers (SIOCON)...................................................................................................16-2 SIO Pre-Scaler Register (SIOPS)..................................................................................................16-3 SIO Block Diagram..............................................................................................................................16-3 Serial I/O Timing Diagram (SIO) ....................................................................................................16-4 Chapter 17 Electrical Data Overview .............................................................................................................................................17-1 Chapter 18 Mechanical Data Overview .............................................................................................................................................18-1 Chapter 19 S3F94A5 Flash MCU Overview .............................................................................................................................................19-1 Operating Mode Characteristics....................................................................................................19-5 Chapter 20 Development Tools Overview .............................................................................................................................................20-1 SHINE ........................................................................................................................................20-1 SAMA Assembler........................................................................................................................20-1 SASM86.....................................................................................................................................20-1 HEX2ROM ..................................................................................................................................20-1 Target Boards .............................................................................................................................20-1 TB94A5 Target Board...................................................................................................................20-3 SMDS2+ Selection (SAM8)..........................................................................................................20-5 Idle LED .....................................................................................................................................20-5 Stop LED....................................................................................................................................20-5 S3C94A5/F94A5 MICROCONTROLLER ix List of Figures Figure Number 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 Title Page Number Block Diagram ....................................................................................................1-3 S3C94A5/F94A5 Pin Assignments (44-QFP-1010B)...............................................1-4 S3C94A5/F94A5 Pin Assignments (42-SDIP-600) ..................................................1-5 Pin Circuit Type B (nRESET) ................................................................................1-8 Pin Circuit Type E ...............................................................................................1-8 Pin Circuit Type E-2 (P5.1-P5.6) ..........................................................................1-9 Pin Circuit Type E-4 (P1, P4.2-P4.6) ....................................................................1-9 Pin Circuit Type F-16 (P2, P5.0) ...........................................................................1-10 Pin Circuit Type F-16A (P3, P4.0, P4.1, P4.7)........................................................1-10 S3C94A5/F94A5 Program Memory Address Space................................................2-2 Smart Option ......................................................................................................2-4 Internal Register File Organization.........................................................................2-5 16-Bit Register Pairs............................................................................................2-6 Stack Operations ................................................................................................2-7 Register Addressing ............................................................................................3-2 Working Register Addressing ...............................................................................3-2 Indirect Register Addressing to Register File..........................................................3-3 Indirect Register Addressing to Program Memory ...................................................3-4 Indirect Working Register Addressing to Register File.............................................3-5 Indirect Working Register Addressing to Program or Data Memory...........................3-6 Indexed Addressing to Register File ......................................................................3-7 Indexed Addressing to Program or Data Memory with Short Offset ...........................3-8 Indexed Addressing to Program or Data Memory with Long Offset............................3-9 Direct Addressing for Load Instructions..................................................................3-10 Direct Addressing for Call and Jump Instructions ....................................................3-11 Relative Addressing .............................................................................................3-12 Immediate Addressing .........................................................................................3-12 S3C94A5/F94A5 MICROCONTROLLER xi List of Figures (Continued) Figure Number 4-1 5-1 5-2 5-3 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 Title Page Number Register Description Format .................................................................................4-4 S3C9-Series Interrupt Type...................................................................................5-1 Interrupt Function Diagram ...................................................................................5-2 S3C94A5/F94A5 Interrupt Structure ......................................................................5-5 System Flags Register (FLAGS)...........................................................................6-4 Crystal/Ceramic Oscillator(fx)...............................................................................7-2 External Oscillator(fx) ..........................................................................................7-2 RC Oscillator(fx)..................................................................................................7-2 External RC Oscillator(fx).....................................................................................7-2 Internal RC Oscillator(fx) ......................................................................................7-2 System Clock Circuit Diagram..............................................................................7-3 System Clock Control Register (CLKCON).............................................................7-4 STOP Control Register (STPCON) ........................................................................7-5 S3C94A5/F94A5 I/O Port Data Register Format .....................................................9-2 Port 1 Control Register, High Byte (P1CONH) ........................................................9-4 Port 1 Control Register, Low Byte (P1CONL) .........................................................9-4 Port 1 Interrupt Control Register (P1INT) ................................................................9-5 Interrupt Pending Register 1 (INTPND1) .................................................................9-5 Port 1 Interrupt Edge Selection Register, High Byte (P1EDGEH) .............................9-6 Port 1 Interrupt Edge Selection Register, Low Byte (P1EDGEL)...............................9-6 Port 2 Control Register, High Byte (P2CONH) ........................................................9-7 Port 2 Control Register, Low Byte (P2CONL) .........................................................9-8 Port 2 Pull-up Control Register (P2PUR)................................................................9-8 Port 3 Control Register, High Byte (P3CONH) ........................................................9-10 Port 3 Control Register, Low Byte (P3CONL) .........................................................9-11 Port 3 Interrupt Control Register (P3INT) ................................................................9-12 Interrupt Pending Register 2 (INTPND2) .................................................................9-12 Port 3 Interrupt Edge Selection Register, High Byte (P3EDGEH) .............................9-13 Port 3 Interrupt Edge Selection Register, Low Byte (P3EDGEL)...............................9-13 Port 3 Pull-up Control Register (P3PUR)................................................................9-14 Port 4 Control Register, High Byte (P4CONH) ........................................................9-16 Port 4 Control Register, Middle Byte (P4CONM).....................................................9-16 Port 4 Control Register, Low Byte (P4CONL) .........................................................9-17 Port 4 Pull-up Control Register (P4PUR)................................................................9-17 Port 4 and 5 Interrupt Control Register (P4n5INT)....................................................9-18 Interrupt Pending Register 2 (INTPND2) .................................................................9-18 Port 5 Control Register, High-Byte (P5CONH) ........................................................9-19 Port 5 Control Register, Low-Byte (P5CONL) .........................................................9-20 Port 4 and 5 Interrupt Control Register (P4n5INT)....................................................9-20 Interrupt Pending Register 2 (INTPND2) .................................................................9-21 xii S3C94A5/F94A5 MICROCONTROLLER List of Figures (Continued) Figure Number 10-1 10-2 11-1 11-2 11-3 11-4 11-5 11-6 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 13-4 13-5 13-6 14-1 14-2 Title Page Number Basic Timer Control Register (BTCON) ..................................................................10-2 Basic Timer Block Diagram ..................................................................................10-4 Timer 0 Control Register (T0CON) .........................................................................11-2 Interrupt Pending Register 3 (INTPND3) .................................................................11-3 Simplified Timer 0 Function Diagram: Interval Timer Mode .......................................11-4 Simplified Timer 0 Function Diagram: PWM Mode ..................................................11-5 Simplified Timer 0 Function Diagram: Capture Mode ...............................................11-6 Timer 0 Block Diagram.........................................................................................11-7 Timer 1 Control Register (T1CON) .........................................................................12-2 Interrupt Pending Register 3 (INTPND3) .................................................................12-3 Simplified Timer 1 Function Diagram: Interval Timer Mode .......................................12-4 Simplified Timer 1 Function Diagram: PWM Mode ..................................................12-5 Simplified Timer 1 Function Diagram: Capture Mode ...............................................12-6 Timer 1 Block Diagram.........................................................................................12-7 Timer 2 Control Register (T2CON) .........................................................................13-2 Interrupt Pending Register 3 (INTPND3) .................................................................13-3 Simplified Timer 2 Function Diagram: Interval Timer Mode .......................................13-4 Simplified Timer 2 Function Diagram: PWM Mode ..................................................13-5 Simplified Timer 2 Function Diagram: Capture Mode ...............................................13-6 Timer 2 Block Diagram.........................................................................................13-7 Watch Timer Control Register (WTCON)................................................................14-2 Watch Timer Circuit Diagram................................................................................14-3 S3C94A5/F94A5 MICROCONTROLLER xiii List of Figures (Continued) Figure Number 15-1 15-2 15-3 15-4 16-1 16-2 16-3 16-4 16-5 17-1 17-2 17-3 17-4 17-5 17-6 17-7 18-1 18-2 19-1 19-2 19-3 20-1 20-2 20-3 20-4 20-5 Title Page Number A/D Converter Control Register (ADCON)...............................................................15-2 A/D Converter Data Register (ADDATAH/ADDATAL)...............................................15-3 A/D Converter Functional Block Diagram ...............................................................15-4 Recommended A/D Converter Circuit for Highest Absolute Accuracy........................15-5 Serial I/O Module Control Register (SIOCON).........................................................16-2 SIO Prescaler Register (SIOPS) ...........................................................................16-3 SIO Functional Block Diagram..............................................................................16-3 Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0).................16-4 Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) .................16-4 Stop Mode Release Timing When Initiated by an External Interrupt ..........................17-6 Stop Mode Release Timing When Initiated by a RESET..........................................17-7 Input Timing for External Interrupts ........................................................................17-9 Input Timing for nRESET......................................................................................17-10 Serial Data Transfer Timing...................................................................................17-10 Clock Timing Measurement at XIN .........................................................................17-12 Operating Voltage Range .....................................................................................17-14 42-SDIP-600 Package Dimensions........................................................................18-1 44-QFP-1010B Package Dimensions ....................................................................18-2 S3F94A5 Pin Assignments (44-QFP-1010B)..........................................................19-2 S3F94A5 Pin Assignments (42-SDIP-600) .............................................................19-3 Operating Voltage Range .....................................................................................19-7 SMDS Product Configuration (SMDS2+)................................................................20-2 TB94A5 Target Board Configuration.......................................................................20-3 Connectors (J101, J102) for TB94A5......................................................................20-6 S3C94A5 Probe Adapter for 42-SDIP Package.......................................................20-7 S3C94A5 Probe Adapter for 44-QFP Package........................................................20-7 xiv S3C94A5/F94A5 MICROCONTROLLER List of Tables Table Number 1-1 4-1 6-1 6-2 6-3 6-4 6-5 6-6 8-1 9-1 9-2 17-1 17-2 17-3 17-4 17-5 17-6 17-7 17-8 17-9 17-10 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 Title Page Number Pin Descriptions ..................................................................................................1-6 System and Peripheral Control Registers...............................................................4-2 Instruction Group Summary ..................................................................................6-2 Flag Notation Conventions ....................................................................................6-5 Instruction Set Symbols.......................................................................................6-5 Instruction Notation Conventions ...........................................................................6-6 Opcode Quick Reference .....................................................................................6-7 Condition Codes ..................................................................................................6-9 Register Values after RESET................................................................................8-4 S3C94A5 Port Configuration Overview....................................................................9-1 Port Data Register Summary ................................................................................9-2 Absolute Maximum Ratings..................................................................................17-2 D.C. Electrical Characteristics..............................................................................17-3 Data Retention Supply Voltage in Stop Mode.........................................................17-6 Input/Output Capacitance.....................................................................................17-7 A.C. Electrical Characteristics..............................................................................17-8 A/D Converter Electrical Characteristics ................................................................17-9 Main Oscillation Characteristics............................................................................17-11 Main Oscillator Stabilization Time .........................................................................17-12 External RC Oscillation (Mode 2) Characteristics ...................................................17-13 Internal RC Oscillation Characteristics...................................................................17-13 Descriptions of Pins Used to Read/Write the Flash ROM ........................................19-4 Comparison of S3F94A5 and S3C94A5 Features....................................................19-4 Operating Mode Selection Criteria.........................................................................19-5 D.C. Electrical Characteristics..............................................................................19-6 Power Selection Settings for TB94A5....................................................................20-4 Smart Option Switch Settings for TB94A5..............................................................20-4 The SMDS2+ Tool Selection Setting .....................................................................20-5 Using Single Header Pins as the Input Path for External Trigger Sources..................20-5 S3C94A5/F94A5 MICROCONTROLLER xv List of Programming Tips Description Page Number Address Spaces Chapter 2: Addressing the Common Working Register Area ................................................................................2-6 Standard Stack Operations Using PUSH and POP.............................................................................2-8 Chapter 5: Interrupt Structure How to clear an interrupt pending bit..................................................................................................5-6 Chapter 7: Clock Circuits How to Use Stop Instruction .............................................................................................................7-5 S3C94A5/F94A5 MICROCONTROLLER xvii List of Register Descriptions Register Identifier ADCON BTCON CLKCON FLAGS INTPND1 INTPND2 INTPND3 P1CONH P1CONL P1INT P1EDGEH P1EDGEL P2CONH P2CONL P2PUR P3CONH P3CONL P3INT P3EDGEH P3EDGEL P3PUR P4CONH P4CONM P4CONL P4n5INT P4PUR P5CONH P5CONL SIOCON STPCON SYM T0CON T1CON T2CON WTCON Full Register Name Page Number A/D Converter Control Register .............................................................................4-5 Basic Timer Control Register ................................................................................4-6 System Clock Control Register.............................................................................4-7 System Flags Register ........................................................................................4-8 Interrupt Pending Register 1 .................................................................................4-9 Interrupt Pending Register 2 .................................................................................4-10 Interrupt Pending Register 3 .................................................................................4-11 Port 1 Control Register (High Byte) .......................................................................4-12 Port 1 Control Register (Low Byte) ........................................................................4-13 Port 1 Interrupt Control Register............................................................................4-14 Port 1 Interrupt Edge Selection Register (High Byte)...............................................4-15 Port 1 Interrupt Edge Selection Register (Low Byte)................................................4-16 Port 2 Control Register (High Byte) .......................................................................4-17 Port 2 Control Register (Low Byte) ........................................................................4-18 Port 2 Pull-up Control Register..............................................................................4-19 Port 3 Control Register (High Byte) .......................................................................4-20 Port 3 Control Register (Low Byte) ........................................................................4-21 Port 3 Interrupt Control Register............................................................................4-22 Port 3 Interrupt Edge Selection Register (High Byte)...............................................4-23 Port 3 Interrupt Edge Selection Register (Low Byte)................................................4-24 Port 3 Pull-up Control Register..............................................................................4-25 Port 4 Control Register (High Byte) .......................................................................4-26 Port 4 Control Register (Middle Byte) ....................................................................4-27 Port 4 Control Register (Low Byte) ........................................................................4-28 Port 4 and 5 Interrupt Control Register...................................................................4-29 Port 4 Pull-up Control Register..............................................................................4-30 Port 5 Control Register (High Byte) .......................................................................4-31 Port 5 Control Register (Low Byte) ........................................................................4-32 SIO Control Register............................................................................................4-33 Stop Control Register...........................................................................................4-34 System Mode Register ........................................................................................4-35 Timer 0 Control Register.......................................................................................4-36 Timer 1 Control Register.......................................................................................4-37 Timer 2 Control Register.......................................................................................4-38 Watch Timer Control Register...............................................................................4-39 S3C94A5/F94A5 MICROCONTROLLER xix List of Instruction Descriptions Instruction Mnemonic ADC ADD AND CALL CCF CLR COM CP DEC DI EI IDLE INC IRET JP JR LD LDC/LDE LDCD/LDED LDCI/LDEI NOP OR POP PUSH RCF RET RL RLC RR RRC SBC SCF SRA STOP SUB TCM TM XOR Full Instruction Name Page Number Add With Carry ...................................................................................................6-11 Add....................................................................................................................6-12 Logical AND........................................................................................................6-13 Call Procedure ....................................................................................................6-14 Complement Carry Flag .......................................................................................6-15 Clear ..................................................................................................................6-16 Complement .......................................................................................................6-17 Compare.............................................................................................................6-18 Decrement ..........................................................................................................6-19 Disable Interrupts ................................................................................................6-20 Enable Interrupts .................................................................................................6-21 Idle Operation......................................................................................................6-22 Increment ...........................................................................................................6-23 Interrupt Return ...................................................................................................6-24 Jump..................................................................................................................6-25 Jump Relative......................................................................................................6-26 Load...................................................................................................................6-27 Load Memory ......................................................................................................6-29 Load Memory and Decrement ...............................................................................6-31 Load Memory and Increment ................................................................................6-32 No Operation.......................................................................................................6-33 Logical OR..........................................................................................................6-34 Pop From Stack..................................................................................................6-35 Push To Stack ....................................................................................................6-36 Reset Carry Flag .................................................................................................6-37 Return ................................................................................................................6-38 Rotate Left ..........................................................................................................6-39 Rotate Left Through Carry.....................................................................................6-40 Rotate Right........................................................................................................6-41 Rotate Right Through Carry ..................................................................................6-42 Subtract With Carry .............................................................................................6-43 Set Carry Flag.....................................................................................................6-44 Shift Right Arithmetic...........................................................................................6-45 Stop Operation....................................................................................................6-46 Subtract .............................................................................................................6-47 Test Complement Under Mask..............................................................................6-48 Test Under Mask.................................................................................................6-49 Logical Exclusive OR...........................................................................................6-50 S3C94A5/F94A5 MICROCONTROLLER xxi S3C94A5/F94A5 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports Flash device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations. S3C94A5/F94A5 MICROCONTROLLER The S3C94A5 can be used for dedicated control functions in a variety of applications, and is especially designed for application with printer or etc. The S3C94A5/F94A5 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core. Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C94A5/F94A5 has 16K-byte of program ROM, and 368-byte of RAM (including 16-byte of working register). Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core: -- 5 configurable I/O ports including ports -- 15-bit programmable pins for external interrupts -- One 8-bit basic timer for oscillation stabilization and watch-dog functions -- Two 16-bit timer/counters and one 8-bit timer/counter with selectable operating modes -- Watch timer for real time -- 16 channel A/D converter -- 8-bit serial I/O interface FLASH The S3F94A5 microcontroller is available in Flash version. S3C94A5 microcontroller has an on-chip 16K-byte masked ROM. The S3F94A5 is comparable to S3C94A5, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C94A5/F94A5 FEATURES CPU * SAM88RCRI CPU core 8-bit Serial I/O Interface * * * * 8-bit transmit/receive mode 8-bit receive mode LSB-first or MSB-first transmission selectable Internal or external clock source Memory * * 16k x 8 bits program memory (ROM) 368 x 8 bits data memory (RAM) Instruction Set * * 41 instructions Idle and Stop instructions added for power-down modes A/D Converter * * * 10-bit converter resolution 50us conversion speed at 1MHz fADC clock 16-channel 34 I/O Pins * High sink current (20mA at 3.3V) Two Power-Down Modes * * Idle mode: only CPU clock stops Stop mode: system clock and CPU clock stop Interrupts * * 23 interrupt source and 1 vector One interrupt level Oscillation Sources * * * Crystal, ceramic, or RC for main clock (Internal or external RC oscillation) System clock frequency: 0.4 MHz - 12 MHz CPU clock output 8-Bit Basic Timer * * Watchdog timer function 4 kinds of clock source Instruction Execution Times 16-Bit Timer/Counter 0 * * External event counter PWM and capture function Operating Voltage Range * * * 2.0 V to 5.5 V at 4.2 MHz 2.7 V to 5.5 V at 8 MHz 3.0 V to 5.5 V at 12 MHz * 333nS at 12 MHz fx (minimum) 16-Bit Timer/Counter 1 * * Programmable 16-bit interval timer PWM and capture function Operating Temperature Range 8-Bit Timer/Counter 2 * * Programmable 8-bit interval timer PWM and capture function Package Type * 44-pin QFP, 42-pin SDIP * -25 C to +85 C Watch Timer * * Interval time: 3.91mS, 0.25S, 0.5S, and 1S at 4.19 MHz 0.5/1/2/4 kHz Selectable buzzer output Smart Option * Oscillator type selectable by ROM option (ROM address 3FH) 1-2 S3C94A5/F94A5 PRODUCT OVERVIEW BLOCK DIAGRAM nRESET TEST XOUT VDD1 VDD2 VSS1 VSS2 CLO INT XIN T0PWM/T0OUT/P3.3 T0CAP/P3.4 T0CLK/P3.5 16-Bit Timer/ Counter0 16-Bit Timer/ Counter1 8-Bit Timer/ Counter2 SAM88RCRI CPU Port I/O and Interrupt Control Watch Dog Timer Basic Timer T1OUT/T1PWM/P4.0 T1CAP/P4.2 Watch Timer BUZ/P3.1 SO/P4.4 SI/P4.5 SCK/P4.6 AD0 - AD15 AVREF AVSS P4.0/AD12/T1OUT/T1PWM P4.1/AD13/T2OUT/T2PWM P4.2/T1CAP P4.3/T2CAP P4.4/SO P4.5/SI P4.6/SCK P4.7/AD14/INT P5.0/AD15/INT P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 T2OUT/T2PWM/P4.1 T2CAP/P4.3 P1.0/INT P1.1/INT P1.2/INT P1.3/INT P1.4/INT P1.5/INT P1.6/INT P2.0 - P2.5/ AD0 - AD5 P3.0/AD6/CLO/INT P3.1/AD7/BUZ/INT P3.2/AD8/INT P3.3/AD9/T0OUT/T0PWM/INT P3.4/AD10/T0CAP/INT P3.5/AD11/T0CLK/INT SIO A/D Converter I/O Port 1 I/O Port 2 16-Kbyte ROM 368-Byte Register File I/O Port 4 I/O Port 3 I/O Port 5 Figure 1-1. Block Diagram 1-3 PRODUCT OVERVIEW S3C94A5/F94A5 PIN ASSIGNMENTS P1.1/INT P1.2/INT P1.3/INT P1.4/INT P1.5/INT P1.6/INT P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 P1.0/INT VDD1 XIN XOUT VSS1 nRESET TEST P5.6 P5.5 P5.4 P5.3 S3C94A5 S3F94A5 (44-QFP-1010B) P5.2 P5.1 P5.0/AD15/INT P4.7/AD14/INT P4.6/SCK P4.5/SI P4.4/SO P4.3/T2CAP P4.2/T1CAP P4.1/AD13/T2OUT/T2PWM P4.0/AD12/T1OUT/T1PWM Figure 1-2. S3C94A5/F94A5 Pin Assignments (44-QFP-1010B) 1-4 P2.5/AD5 AVREF AVSS P3.0/AD6/CLO/INT P3.1/AD7/BUZ/INT P3.2/AD8/INT P3.3/AD9/T0OUT/T0PWM/INT P3.4/AD10/T0CAP/INT P3.5/AD11/T0CLK/INT VDD2 VSS2 12 13 14 15 16 17 18 19 20 21 22 S3C94A5/F94A5 PRODUCT OVERVIEW P1.6/INT P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVREF AVSS P3.0/AD6/CLO/INT P3.1/AD7/BUZ/INT P3.2/AD8/INT P3.3/AD9/T0OUT/T0PWM/INT P3.4/AD10/T0CAP/INT P3.5/AD11/T0CLK/INT P4.0/AD12/T1OUT/T1PWM P4.1/AD13/T2OUT/T2PWM P4.2/T1CAP P4.3/T2CAP P4.4/SO P4.5/SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P1.5/INT P1.4/INT P1.3/INT P1.2/INT P1.1/INT P1.0/INT VDD1 XIN XOUT VSS1 nRESET TEST P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0/AD15/INT P4.7/AD14/INT P4.6/SCK Figure 1-3. S3C94A5/F94A5 Pin Assignments (42-SDIP-600) (42-SDIP-600) S3C94A5 S3F94A5 1-5 PRODUCT OVERVIEW S3C94A5/F94A5 PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1-P5.6 NOTE: Pin Type I/O Pin Description 1-bit programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pullups. Circuit Number E-4 Pin Numbers 44(37) 1(38) 2(39) 3(40) 4(41) 5(42) 6(1) 7(2) 8(3) 9(4) 10(5) 11(6) 12(7) 15(10) 16(11) 17(12) 18(13) 19(14) 20(15) Share Pins INT INT INT INT INT INT INT AD0 AD1 AD2 AD3 AD4 AD5 AD6/CLO/INT AD7/BUZ/INT AD8/INT AD9/T0OUT/ T0PWM/INT AD10/T0CAP/INT AD11/T0CLK/INT AD12/T1OUT/ T1PWM AD13/T2OUT/ T2PWM T1CAP T2CAP SO SI SCK AD14/INT AD15/INT - I/O 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. F-16 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pullups. F-16A I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, opendrain output and software assignable pullups. F-16A F-16A E-4 E-4 E-4 E-4 E-4 F-16A 23(16) 24(17) 25(18) 26(19) 27(20) 28(21) 29(22) 30(23) 31(24) 32-37(25-30) I/O 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. F-16 E-2 Parentheses indicate pin number for 42-SDIP-600 package. 1-6 S3C94A5/F94A5 PRODUCT OVERVIEW Table 1-1. Pin Descriptions (Continued) Pin Names VDD1, VSS1 VDD2, VSS2 XOUT, XIN TEST nRESET INT Pin Type - Pin Description Power input pins for internal power block Circuit Number - Pin Numbers 43,40(36,33) 21,22(-) 41,42(34,35) 38(31) 39(32) 44,1-6 (37-42,1) 15-20(10-15) 30(23) 31(24) 20(15) 19(14) 18(13) 18(13) 25(18) 23(16) 23(16) 26(19) 24(17) 24(17) 7-12(2-7) 15-20(10-15) 23,24,30 (16,17,23) 31(24) 13(8) 14(9) 16(11) 15(10) 29(22) 28(21) 27(20) Share Pins - - - I I/O Oscillator pins for system clock Chip test input pin Hold GND when the device is operating nRESET signal input pin. Schmitt trigger input with internal pull-up resistor. External interrupts input. - - B E-4 F-16A F-16A F-16 - - - P1.0-P1.6 P3.0-P3.5 P4.7 P5.0 P3.5 P3.4 P3.3 P3.3 P4.2 P4.0 P4.0 P4.3 P4.1 P4.1 P2.0-P2.5 P3.0-P3.5 P4.0,P4.1, P4.7 P5.0 - - P3.1 P3.0 P4.6 P4.5 P4.4 T0CLK T0CAP T0OUT T0PWM T1CAP T1OUT T1PWM T2CAP T2OUT T2PWM AD0-AD5 AD6-AD11 AD12,13,14 AD15 AVREF AVSS BUZ CLO SCK SI SO NOTE: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Timer 0 external clock input Timer 0 capture input Timer 0 clock output Timer 0 PWM output Timer 1 capture input Timer 1 clock output Timer 1 PWM input Timer 2 capture input Timer 2 clock output Timer 2 PWM output Analog input pins for A/D converts module F-16A F-16A F-16A F-16A E-4 F-16A F-16A E-4 F-16A F-16A F-16 F-16A F-16A F-16 - - I/O I/O I/O A/D converter reference voltage A/D converter ground Buzzer signal output CPU clock output Serial clock, serial data input, serial data output - - F-16A F-16A E-4 Parentheses indicate pin number for 42-SDIP-600 package. 1-7 PRODUCT OVERVIEW S3C94A5/F94A5 PIN CIRCUIT DIAGRAMS VDD Pull-Up Resistor nRESET Noise Filter Figure 1-4. Pin Circuit Type B (nRESET) VDD Open-Drain Data Output Output Disable Figure 1-5. Pin Circuit Type E 1-8 S3C94A5/F94A5 PRODUCT OVERVIEW VDD Pull-up Resistor Resistor Enable VDD Open-Drain Data Output Disable I/O Figure 1-6. Pin Circuit Type E-2 (P5.1-P5.6) VDD Pull-up Resistor Pull-up Enable VDD Open-Drain Data Output Disable I/O Figure 1-7. Pin Circuit Type E-4 (P1, P4.2-P4.6) 1-9 PRODUCT OVERVIEW S3C94A5/F94A5 VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data Output Disable Circuit Type E I/O ADEN AD Select Data To ADC Figure 1-8. Pin Circuit Type F-16 (P2, P5.0) VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data Output Disable Circuit Type E I/O ADEN AD Select Data To ADC Figure 1-9. Pin Circuit Type F-16A (P3, P4.0, P4.1, P4.7) 1-10 S3C94A5/F94A5 ADDRESS SPACES 2 OVERVIEW ADDRESS SPACES The S3C94A5/F94A5 microcontroller has two kinds of address space: -- Program memory (ROM) -- Internal register file A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file. The S3C94A5 has 16K bytes of mask-programmable program memory on-chip. The S3C94A5/F94A5 microcontroller has 368 bytes general-purpose registers in its internal register file 64 bytes in the register file are mapped for system and peripheral control functions. 2-1 ADDRESS SPACES S3C94A5/F94A5 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C94A5 has 16K bytes of mask-programable program memory. The program memory address range is therefore 0H-3FFFH. The first 2 bytes of the ROM (0000H- 0001H) are an interrupt vector address. The program reset address in the ROM is 0100H. (Decimal) 16,386 (Hex) 3FFFH 16K bytes Internal Program Memory Area 256 2 1 0 Program Start 0100H 0002H Interrupt Vector 0001H 0000H Figure 2-1. S3C94A5/F94A5 Program Memory Address Space 2-2 S3C94A5/F94A5 ADDRESS SPACES SMART OPTION Smart option is the ROM option for starting condition of the chip. The ROM addresses used by smart option are from 003CH to 003FH. The S3C94A5 only use 003FH and ROM address 003CH, 003DH, 003EH is not used. For example, if you program as below: ORG DB 003FH 01H ; Select internal RC oscillation If you don't program any values in these option areas, then the default value is "1". In these cases, the address 003CH, 003DH, 003EH would be the value of "FFH". 2-3 ADDRESS SPACES S3C94A5/F94A5 ROM Address: 003CH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not Used ROM Address: 003DH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not Used ROM Address: 003EH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not Used ROM Address: 003FH MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not Used Oscillator selection bits: 000 = External crystal, ceramic, External RC oscillation mode 1 001 = Internal RC oscillation 100 = fERC/1 (External RC oscillation mode 2) 101 = fERC/2 (External RC oscillation mode 2) 110 = fERC/4 (External RC oscillation mode 2) 111 = fERC/8 (External RC oscillation mode 2) NOTE: The value of unused bits of 3FH is don't care. Figure 2-2. Smart Option 2-4 S3C94A5/F94A5 ADDRESS SPACES REGISTER ARCHITECTURE The upper 80 bytes of the S3C94A5/F94A5's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 176 bytes of internal register file (00H-AFH) is called the general purpose register space. For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00H-BFH). This register file expansion is implemented by page 1 in the S3C94A5/F94A5. FFH Peripheral Control Registers E0H DFH D0H CFH C0H BFH B0H AFH 80 Bytes of Common Area System Control Registers Working Registers Peripheral Control Registers AFH 176 Bytes ~ General Purpose Register File and Stack Area 176 Bytes General Purpose Register File 00H 00H (Page 0) (Page 1) Figure 2-3. Internal Register File Organization 2-5 ADDRESS SPACES S3C94A5/F94A5 COMMON WORKING REGISTER AREA (C0H-CFH) The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. The Register (R) addressing mode can be used to access this area Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register. MSB Rn LSB Rn + 1 n = Even address Figure 2-4. 16-Bit Register Pairs F PROGRAMMING TIP -- Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H-CFH, using working register addressing mode only. Examples: 1. LD 0C2H,40H ; Invalid addressing mode! ; R2 (C2H) the value in location 40H ; Invalid addressing mode! ; R3 (C3H) R3 + 45H Use working register addressing instead: LD 2. ADD R2,40H 0C3H,#45H Use working register addressing instead: ADD R3,#45H 2-6 S3C94A5/F94A5 ADDRESS SPACES SYSTEM STACK S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C94A5/F94A5 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-5. High Address PCL PCL Top of stack PCH PCH Top of stack Flags Stack contents after an interrupt Stack contents after a call instruction Low Address Figure 2-5. Stack Operations STACK POINTER (SP) Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3C94A5/F94A5, the SP must be initialized to an 8-bit value in the range 00H-B7H. NOTE In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area. 2-7 ADDRESS SPACES S3C94A5/F94A5 F PROGRAMMING TIP -- Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD * * * SP,#0B8H ; SP B8H (Normally, the SP is set to 0B8H by the ; initialization routine) PUSH PUSH PUSH PUSH * * * SYM WTCON 20H R3 ; ; ; ; Stack address 0B7H Stack address 0B6H Stack address 0B5H Stack address 0B4H SYM WTCON 20H R3 POP POP POP POP R3 20H WTCON SYM ; ; ; ; R3 Stack address 0B4H 20H Stack address 0B5H WTCON Stack address 0B6H SYM Stack address 0B7H 2-8 S3C94A5/F94A5 ADDRESSING MODES 3 OVERVIEW ADDRESSING MODES Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows: -- Register (R) -- Indirect Register (IR) -- Indexed (X) -- Direct Address (DA) -- Relative Address (RA) -- Immediate (IM) 3-1 ADDRESSING MODES S3C94A5/F94A5 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2). Program Memory 8-bit Register File Address Register File dst OPCODE One-Operand Instruction (Example) Point to One Rigister in Register File Value used in Instruction Execution OPERAND Sample Instruction: DEC CNTR ; Where CNTR is the label of an 8-bit register address Figure 3-1. Register Addressing Register File CFH Program Memory 4-Bit Working Register 4 LSBs Point to the Woking Register (1 of 16) . . . . OPERAND C0H dst src OPCODE Two-Operand Instruction (Example) Sample Instruction: ADD R1, R2 ; Where R1 = C1H and R2 = C2H Figure 3-2. Working Register Addressing 3-2 S3C94A5/F94A5 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Program Memory 8-Bit Register File Address One-Operand Instruction (Example) Register File dst OPCODE ADDRESS Point to One Rigister in Register File Address of Operand used by Instruction Value used in Instruction Execution OPERAND Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-Bit register address Figure 3-3. Indirect Register Addressing to Register File 3-3 ADDRESSING MODES S3C94A5/F94A5 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory REGISTER PAIR Points to Rigister Pair 16-Bit Address Points to Program Memory dst OPCODE Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4. Indirect Register Addressing to Program Memory 3-4 S3C94A5/F94A5 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File CFH Program Memory 4-Bit Working Register Address 4 LSBs Point to the Woking Register (1 of 16) . . . . OPERAND C0H dst src OPCODE Sample Instruction: OR R6, @R2 Value used in Instruction OPERAND Figure 3-5. Indirect Working Register Addressing to Register File 3-5 ADDRESSING MODES S3C94A5/F94A5 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File CFH Program Memory 4-Bit Working Register Address dst src OPCODE Next 3 Bits Point to Working Register Pair (1 of 8) LSB Selects . . . . Register Pair C0H 16-Bit address points to program memory or data memory Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Value used in Instruction OPERAND Sample Instructions: LCD LDE LDE R5,@RR6 R3,@RR14 @RR4, R8 ; Program memory access ; External data memory access ; External data memory access Figure 3-6. Indirect Working Register Addressing to Program or Data Memory 3-6 S3C94A5/F94A5 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of -128 to +127. This applies to external memory accesses only (see Figure 3-8). For register file addressing, an 8-bit base address provi ded by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented. Register File ~ Value used in Instruction OPERAND ~ + Program Memory Base Address dst src OPCODE 4 LSBs Point to One of the Woking Register (1 of 16) ~ INDEX ~ Two-Operand Instruction Example Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value Figure 3-7. Indexed Addressing to Register File 3-7 ADDRESSING MODES S3C94A5/F94A5 INDEXED ADDRESSING MODE (Continued) Program Memory 4-Bit Working Register Address XS (OFFSET) dst src OPCODE NEXT 3 Bits Point to Working Register Pair (1 of 8) Register File Register Pair 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory Value used in Instruction 16-Bits OPERAND Sample Instructions: LDC LDE R4, #04H[RR2] R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset 3-8 S3C94A5/F94A5 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory XLH (OFFSET) XLL (OFFSET) dst src OPCODE Register File 4-Bit Working Register Address NEXT 3 Bits Point to Working Register Pair (1 of 8) LSB Selects Register Pair 16-Bit address added to offset + 8-Bits 16-Bits Program Memory or Data Memory 16-Bits Sample Instructions: LDC R4, #1000H[RR2] #1000H) LDE R4, #1000H[RR2] OPERAND Value used in Instruction ; The values in the program address (RR2 + are loaded into register R4. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset 3-9 ADDRESSING MODES S3C94A5/F94A5 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Program or Data Memory Program Memory Memory Address Used Upper Address Byte Lower Address Byte dst/src "0" or "1" OPCODE LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory Sample Instructions: LDC LDE R5,1234H R5,1234H ; The values in the program address (1234H) are loaded into register R5. ; Identical operation to LDC example, except that external program memory is accessed. Figure 3-10. Direct Addressing for Load Instructions 3-10 S3C94A5/F94A5 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11. Direct Addressing for Call and Jump Instructions 3-11 ADDRESSING MODES S3C94A5/F94A5 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between - 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR. Program Memory Next OPCODE Program Memory Address Used Current Instruction Displacement OPCODE Current PC Value + Signed Displacement Value Sample Instructions: JR ULT,$ + OFFSET ; Where OFFSET is a value in the range + 127 to - 128 Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers. Program Memory OPERAND OPCODE (The Operand value is in the instruction) Sample Instruction: LD R0,#0AAH Figure 3-13. Immediate Addressing 3-12 S3C94A5/F94A5 CONTROL REGISTERS 4 OVERVIEW CONTROL REGISTERS In this section, detailed descriptions of the S3C94A5/F94A5 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual. 4-1 CONTROL REGISTERS S3C94A5/F94A5 Table 4-1. System and Peripheral Control Registers Register Name Mnemonic Address Decimal Locations B0H -- B3H are not mapped Timer 0 control register Timer 0 data register (high byte) Timer 0 data register (low byte) Timer 0 counter (high byte) Timer 0 counter (low byte) Timer 1 control resistor Timer 1 data register (high byte) Timer 1 data register (low byte) Timer 1 counter (high byte) Timer 1 counter (low byte) Timer 2 control register Timer 2 data register Timer 2 counter A/D converter control register A/D converter data register (high byte) A/D converter data register (low byte) System clock control register System flags register Interrupt pending register 1 Interrupt pending register 2 Interrupt pending register 3 Stack pointer Watch timer control register T0CON T0DATAH T0DATAL T0CNTH T0CNTL T1CON T1DATAH T1DATAL T1CNTH T1CNTL T2CON T2DATA T2CNT ADCON ADDATAH ADDATAL CLKCON FLAGS INTPND1 INTPND2 INTPND3 SP WTCON Location DBH is not mapped Basic timer control register Basic timer counter BTCON BTCNT Location DEH is not mapped System mode register STOP control register SIO control register SIO data register SIO prescaler register SYM STPCON SIOCON SIODATA SIOPS 223 224 225 226 227 DFH E0H E1H E2H E3H R/W R/W R/W R/W R/W 220 221 DCH DDH R/W R 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH R/W R/W R/W R R R/W R/W R/W R R R/W R/W R R/W R R R/W R/W R/W R/W R/W R/W R/W Hex R/W 4-2 S3C94A5/F94A5 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Continued) Register Name Mnemonic Address Decimal Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register P1 P2 P3 P4 P5 Location E9H is not mapped Port 1 control register (high byte) Port 1 control register (low byte) Port 1 interrupt control register Port 1 interrupt edge selection register (high byte) Port 1 interrupt edge selection register (low byte) Port 2 control register (high byte) Port 2 control register (low byte) Port 2 pull-up control register Port 3 control register (high byte) Port 3 control register (low byte) Port 3 pull-up control register Port 3 interrupt control register Port 3 interrupt edge selection register (high byte) Port 3 interrupt edge selection register (low byte) Port 4 control register (high byte) Port 4 control register (middle byte) Port 4 control register (low byte) Port 4 and 5 interrupt control register Port 4 pull-up control register Port 5 control register (high byte) Port 5 control register (low byte) P1CONH P1CONL P1INT P1EDGEH P1EDGEL P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P3INT P3EDGEH P3EDGEL P4CONH P4CONM P4CONL P4n5INT P4PUR P5CONH P5CONL Location FFH is not mapped 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 228 229 230 231 232 Hex E4H E5H E6H E7H E8H R/W R/W R/W R/W R/W R/W 4-3 CONTROL REGISTERS S3C94A5/F94A5 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or bit function Full Register name mnemonic Register address (hexadecimal) FLAGS - System Flags Register Bit Identifier RESET Value Read/Write .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 x R/W D5H .2 x R/W .1 0 R/W .0 0 R/W Carry Flag (C) 0 1 Operation dose not generate a carry or borrow condition Operation generates carry-out or borrow into high-order bit7 .6 Zero Flag 0 1 Operation result is a non-zero value Operation result is zero .5 Sign Flag 0 1 Operation generates positive number (MSB = "0") Operation generates negative number (MSB = "1") R = Read-only W = Write-only R/W = Read/write ' - ' = Not used Addressing mode or modes you can use to modify register values Description of the effect of specific bit settings RESET value notation: '-' = Not used 'x' = Undetermind value '0' = Logic zero '1' = Logic one Bit number: MSB = Bit 7 LSB = Bit 0 Figure 4-1. Register Description Format 4-4 S3C94A5/F94A5 CONTROL REGISTERS ADCON -- A/D Converter Control Register Bit Identifier RESET Value Read/Write .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R .2 0 R/W .1 0 R/W D1H .0 0 R/W A/D Input Pin Selection Bits 0 0 0 0 AD0 (P2.0) 0 0 0 1 AD1 (P2.1) 0 0 1 0 AD2 (P2.2) 0 0 1 1 AD3 (P2.3) 0 1 0 0 AD4 (P2.4) 0 1 0 1 AD5 (P2.5) 0 1 1 0 AD6 (P3.0) 0 1 1 1 AD7 (P3.1) 1 0 0 0 AD8 (P3.2) 1 0 0 1 AD9 (P3.3) 1 0 1 0 AD10 (P3.4) 1 0 1 1 AD11 (P3.5) 1 1 0 0 AD12 (P4.0) 1 1 0 1 AD13 (P4.1) 1 1 1 0 AD14 (P4.7) 1 1 1 1 AD15 (P5.0) End of Conversion Bit (Read-only) 0 Conversion not complete 1 Conversion complete Clock Source Selection Bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx Start or Enable Bit 0 Disable operation 1 Start operation (automatically disable operation after conversion complete) .3 .2-.1 .0 4-5 CONTROL REGISTERS S3C94A5/F94A5 BTCON -- Basic Timer Control Register Bit Identifier RESET Value Read/Write .7-.4 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W DCH .0 0 R/W Watchdog Timer Enable Bits 1 0 1 0 Disable watchdog function Enable watchdog function Any other value .3-.2 Basic Timer Input Clock Selection Bits 0 0 1 1 0 1 0 1 fxx/4096 fxx/1024 fxx/128 fxx/16 .1 Basic Timer Counter Clear Bit (1) 0 1 No effect Clear the basic timer counter value (BTCNT) .0 Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2) 0 1 No effect Clear clock frequency dividers NOTES: 1. When "1" is written to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0". 2. When "1" is written to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0". 4-6 S3C94A5/F94A5 CONTROL REGISTERS CLKCON -- System Clock Control Register Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 D4H .0 R/W Oscillator IRQ Wake-up Function Bit 0 1 Enable IRQ for main wake-up in power down mode Disable IRQ for main wake-up in power down mode .6-.5 Bits .6-.5 0 Always logic zero .4-.3 CPU Clock (System Clock) Selection Bits 0 0 1 1 0 1 0 1 Divide by 16 (fxx/16) Divide by 8 (fxx/8) Divide by 2 (fxx/2) Non-divided clock (fxx) .2-.0 Bits .2-.0 0 Always logic zero 4-7 CONTROL REGISTERS S3C94A5/F94A5 FLAGS -- System Flags Register Bit Identifier RESET Value Read/Write .7 .7 x R/W .6 x R/W .5 x R/W .4 x R/W .3 - - .2 - - .1 - - - - D5H .0 Carry Flag (C) 0 Operation does not generate a carry or borrow condition .6 Zero Flag (Z) 0 1 Operation result is a non-zero value Operation result is zero .5 Sign Flag (S) 0 1 Operation generates a positive number (MSB = "0") Operation generates a negative number (MSB = "1") .4 Overflow Flag (V) 0 1 Operation result is +127 or -128 Operation result is +127 or -128 .3-.0 Not used for S3C94A5/F94A5 4-8 S3C94A5/F94A5 CONTROL REGISTERS INTPND1 -- Interrupt Pending Register 1 Bit Identifier RESET Value Read/Write .7 .6 .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 D6H .0 R/W Not used for S3C94A5/F94A5 P1.6's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .5 P1.5's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .4 P1.4's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .3 P1.3's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .2 P1.2's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .1 P1.1's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .0 P1.0's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) 4-9 CONTROL REGISTERS S3C94A5/F94A5 INTPND2 -- Interrupt Pending Register 2 Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 D7H .0 R/W P5.0's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .6 P4.7's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .5 P3.5's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .4 P3.4's Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .3 P3.3's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .2 P3.2's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .1 P3.1's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .0 P3.0's Interrupt Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) 4-10 S3C94A5/F94A5 CONTROL REGISTERS INTPND3 -- Interrupt Pending Register 3 Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 D8H .0 R/W Watch Timer Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .6 SIO Interrupt Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .5 Timer 2 Overflow Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .4 Timer 2 Match or Capture Pending Bit 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) .3 Timer 1 Overflow Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .2 Timer 1 Match or Capture Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .1 Timer 0 Overflow Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) .0 Timer 0 Match or Capture Pending Bit 0 1 No interrupt pending (when read), Clear pending bit (when write) Interrupt is pending (when read) 4-11 CONTROL REGISTERS S3C94A5/F94A5 P1CONH -- Port 1 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W EAH .0 0 R/W .7-.6 Not used for S3C94A5/F94A5 .5-.4 P1.6/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up .3-.2 P1.5/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up .1-.0 P1.4/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up 4-12 S3C94A5/F94A5 CONTROL REGISTERS P1CONL -- Port 1 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W EBH .0 0 R/W P1.3/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up .5-.4 P1.2/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up .3-.2 P1.1/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up .1-.0 P1.0/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Schmitt trigger input, pull-up 4-13 CONTROL REGISTERS S3C94A5/F94A5 P1INT-- Port 1 Interrupt Control Register Bit Identifier RESET Value Read/Write .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W ECH .0 0 R/W .7 Not used for S3C94A5/F94A5 .6 P1.6's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .5 P1.5's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .4 P1.4's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .3 P1.3's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .2 P1.2's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .1 P1.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 P1.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt 4-14 S3C94A5/F94A5 CONTROL REGISTERS P1EDGEH -- Port 1 Interrupt Edge Selection Register (High Byte) Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W EDH .0 0 R/W .7-.6 Not used for S3C94A5/F94A5 .5-.4 P1.6's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .3-.2 P1.5's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .1-.0 P1.4's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available 4-15 CONTROL REGISTERS S3C94A5/F94A5 P1EDGEL -- Port 1 Interrupt Edge Selection Register (Low Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W EEH .0 0 R/W P1.3's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .5-.4 P1.2's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .3-.2 P1.1's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .1-.0 P1.0's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available 4-16 S3C94A5/F94A5 CONTROL REGISTERS P2CONH -- Port 2 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W 0 EFH .0 R/W .7-.4 Not used for S3C94A5/F94A5 .3-.2 P2.5/AD5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Alternative function (AD5) .1-.0 P2.4/AD4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Alternative function (AD4) 4-17 CONTROL REGISTERS S3C94A5/F94A5 P2CONL -- Port 2 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F0H R/W P2.3/AD3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Alternative function (AD3) .5-.4 P2.2/AD2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Alternative function (AD2) .3-.2 P2.1/AD1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Alternative function (AD1) .1-.0 P2.0/AD0 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Alternative function (AD0) 4-18 S3C94A5/F94A5 CONTROL REGISTERS P2PUR -- Port 2 Pull-up Control Register Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F1H R/W .7-.6 Not used for S3C94A5/F94A5 .5 P2.5's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .4 P2.4's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .3 P2.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .2 P2.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .1 P2.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .0 P2.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: A pull-up resistor of port 2 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. 4-19 CONTROL REGISTERS S3C94A5/F94A5 P3CONH -- Port 3 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F2H R/W .7 Not used for S3C94A5/F94A5 .6-.5 P3.5/AD11/T0CLK/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (T0CLK) Push-pull output N-channel open-drain output Alternative function (AD11) .4-.3 P3.4/AD10/T0CAP/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (T0CAP) Push-pull output N-channel open-drain output Alternative function (AD10) .2-.0 P3.3/AD9/T0OUT/T0PWM/INT Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (AD9) Alternative function (T0OUT/T0PWM) Not available Other Values 4-20 S3C94A5/F94A5 CONTROL REGISTERS P3CONL -- Port 3 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F3H R/W P3.2/AD8/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (AD8) .5-.3 P3.1/AD7/BUZ/INT Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (AD7) Alternative function (BUZ) Not available Other Values .2-.0 P3.0/AD6/CLO/INT Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (AD6) Alternative function (CLO) Not available Other Values NOTE: CLO is CPU clock output. 4-21 CONTROL REGISTERS S3C94A5/F94A5 P3INT -- Port 3 Interrupt Control Register Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F5H R/W .7-.6 Not used for S3C94A5/F94A5 .5 P3.5's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .4 P3.4's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .3 P3.3's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .2 P3.2's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .1 P3.1's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 P3.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt 4-22 S3C94A5/F94A5 CONTROL REGISTERS P3EDGEH -- Port 3 Interrupt Edge Selection Register (High Byte) Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F6H R/W .7-.4 Not Used for S3C94A5/F94A5 .3-.2 P3.5's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .1-.0 P3.4's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available 4-23 CONTROL REGISTERS S3C94A5/F94A5 P3EDGEL -- Port 3 Interrupt Edge Selection Register (Low Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F7H R/W P3.3's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .5-.4 P3.2's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .3-.2 P3.1's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .1-.0 P3.0's Interrupt State Setting Bit 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available 4-24 S3C94A5/F94A5 CONTROL REGISTERS P3PUR -- Port 3 Pull-up Control Register Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F4H R/W .7-.6 Not used for S3C94A5/F94A5 .5 P3.5's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .4 P3.4's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .3 P3.3's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .2 P3.2's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .1 P3.1's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor .0 P3.0's Pull-up Resistor Enable Bit 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: A pull-up resistor of port 3 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. 4-25 CONTROL REGISTERS S3C94A5/F94A5 P4CONH -- Port 4 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F8H R/W .7-.4 Not used for S3C94A5/F94A5 .3-.2 P4.7/AD14/INT Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (AD14) .1-.0 P4.6/SCK Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (SCK input) Push-pull output N-channel open-drain output Alternative function (SCK output) 4-26 S3C94A5/F94A5 CONTROL REGISTERS P4CONM -- Port 4 Control Register (Middle Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W .0 0 F9H R/W P4.5/SI Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (SI input) Push-pull output N-channel open-drain output Not available .5-.4 P4.4/SO Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (SO output) .3-.2 P4.3/T2CAP Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (T2CAP) Push-pull output N-channel open-drain output Not available .1-.0 P4.2/T1CAP Configuration Bits 0 0 1 1 0 1 0 1 Schmitt trigger input (T1CAP) Push-pull output N-channel open-drain output Not available 4-27 CONTROL REGISTERS S3C94A5/F94A5 P4CONL -- Port 4 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 FAH .0 R/W .7-.6 Not used for S3C94A5/F94A5 .5-.3 P4.1/AD13/T2OUT/T2PWM Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (T2OUT/T2PWM) Alternative function (AD13) Not available Other Values .2-.0 P4.0/AD12/T1OUT/T1PWM Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Schmitt trigger input Push-pull output N-channel open-drain output Alternative function (T1OUT/T1PWM) Alternative function (AD12) Not available Other Values 4-28 S3C94A5/F94A5 CONTROL REGISTERS P4n5INT -- Port 4 and 5 Interrupt Control Register Bit Identifier RESET Value Read/Write .7 - - .6 - - .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W FBH .0 0 R/W .7-.6 Not used for S3C94A5/F94A5 .5 P5.0's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .4 P4.7's Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .3-.2 P5.0's Interrupt State Setting Bits 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available .1-.0 P4.7's Interrupt State Setting Bits 0 0 1 1 0 1 0 1 Falling edge interrupt Rising edge interrupt Both rising and falling edges interrupt Not available 4-29 CONTROL REGISTERS S3C94A5/F94A5 P4PUR -- Port 4 Pull-up Control Register Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W FCH .0 0 R/W P4.7's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.6's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.5's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.4's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.3's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.1's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P4.0's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor A pull-up resistor of port 4 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. .6 .5 .4 .3 .2 .1 .0 NOTE: 4-30 S3C94A5/F94A5 CONTROL REGISTERS P5CONH -- Port 5 Control Register (High Byte) Bit Identifier RESET Value Read/Write .7-.6 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W FDH .0 0 R/W P5.6 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode .5-.4 P5.5 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode .3-.2 P5.4 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode .1-.0 P5.3 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode 4-31 CONTROL REGISTERS S3C94A5/F94A5 P5CONL -- Port 5 Control Register (Low Byte) Bit Identifier RESET Value Read/Write .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 FEH .0 R/W .7 Not Used for S3C94A5/F94A5 .6-.5 P5.2 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode .4-.3 P5.1 Configuration Bits 0 0 1 1 0 1 0 1 Input mode Push-pull output N-channel open-drain output Input, pull-up mode .2-.0 P5.0/AD15/INT Configuration Bits 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Input mode Push-pull output N-channel open-drain output Input, pull-up mode Alternative function (AD15) Not available Other Values 4-32 S3C94A5/F94A5 CONTROL REGISTERS SIOCON -- SIO Control Register Bit Identifier RESET Value Read/Write .7 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W - - E1H .0 SIO Shift Clock Selection Bit 0 1 Internal clock (P.S clock) External clock (SCK) .6 Data Direction Control Bit 0 1 MSB-first mode LSB-first mode .5 SIO Mode Selection Bit 0 1 Receive-only mode Transmit/receive mode .4 Shift Clock Edge Selection Bit 0 1 Tx at falling edges, Rx at rising edges Tx at rising edges, Rx at falling edges .3 SIO Counter Clear and Shift Start Bit 0 1 No action Clear 3-bit counter and start shifting .2 SIO Shift Operation Enable Bit 0 1 Disable shifter and clock counter Enable shifter and clock counter .1 SIO Interrupt Enable Bit 0 1 Disable SIO interrupt Enable SIO interrupt .0 Not used for S3C94A5/F94A5 4-33 CONTROL REGISTERS S3C94A5/F94A5 STPCON -- Stop Control Register Bit Identifier RESET Value Read/Write .7-.0 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 E0H .0 R/W Stop Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Disable stop instruction Other Values NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute. 4-34 S3C94A5/F94A5 CONTROL REGISTERS SYM -- System Mode Register Bit Identifier RESET Value Read/Write .7 DFH .5 - - .4 - - .3 0 R/W .2 0 R/W .1 0 R/W .0 0 R/W .6 - - - - .7-.4 Not used for S3C94A5/F94A5 .3 Global Interrupt Enable Bit 0 1 Global interrupt processing disable (DI instruction) Global interrupt processing enable (EI instruction) .2-.0 Page Selection Bits 0 0 0 0 0 1 Page 0 Page 1 Not available Other Values 4-35 CONTROL REGISTERS S3C94A5/F94A5 T0CON -- Timer 0 Control Register Bit Identifier RESET Value Read/Write .7-.5 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 B4H .0 R/W Timer 0 Input Clock Selection Bits 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/1024 fxx/256 fxx/64 fxx/8 fxx External clock falling edge (T0CLK) External clock rising edge (T0CLK) Counter stop .4-.3 Timer 0 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF & match interrupt can occur) .2 Timer 0 Counter Clear Bit 0 1 No effect Clear the timer 0 counter (when write) .1 Timer 0 Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 Timer 0 Overflow Interrupt Enable Bit 0 1 Disable overflow interrupt Enable overflow interrupt 4-36 S3C94A5/F94A5 CONTROL REGISTERS T1CON -- Timer 1 Control Register Bit Identifier RESET Value Read/Write .7-.5 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W 0 B9H .0 R/W Timer 1 Input Clock Selection Bits 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/1024 fxx/256 fxx/64 fxx/8 fxx Counter stop Not available Other Values .4-.3 Timer 1 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF & match interrupt can occur) .2 Timer 1 Counter Enable Bit 0 1 No effect Clear the timer 1 counter (when write) .1 Timer 1 Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 Timer 1 Overflow Interrupt Enable Bit 0 1 Disable overflow interrupt Enable overflow interrupt 4-37 CONTROL REGISTERS S3C94A5/F94A5 T2CON -- Timer 2 Control Register Bit Identifier RESET Value Read/Write .7-.5 .7 0 R/W .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W BEH .0 0 R/W Timer 2 Input Clock Selection Bits 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 fxx/1024 fxx/256 fxx/64 fxx/8 fxx Counter stop Not available Other Values .4-.3 Timer 2 Operating Mode Selection Bits 0 0 1 1 0 1 0 1 Interval mode Capture mode (capture on rising edge, counter running, OVF can occur) Capture mode (capture on falling edge, counter running, OVF can occur) PWM mode (OVF & match interrupt can occur) .2 Timer 2 Counter Clear Bit 0 1 No effect Clear the timer 2 counter (when write) .1 Timer 2 Match/Capture Interrupt Enable Bit 0 1 Disable interrupt Enable interrupt .0 Timer 2 Overflow Interrupt Enable Bit 0 1 Disable overflow interrupt Enable overflow interrupt 4-38 S3C94A5/F94A5 CONTROL REGISTERS WTCON -- Watch Timer Control Register Bit Identifier RESET Value Read/Write .7 - - .6 0 R/W .5 0 R/W .4 0 R/W .3 0 R/W .2 0 R/W .1 0 R/W DAH .0 - - .7 Not used for S3C94A5/F94A5 .6 Watch Timer Interrupt Enable Bit 0 1 Disable watch timer interrupt Enable watch timer interrupt .5-.4 Buzzer Signal Selection Bits (fx = 4.19 MHz) 0 0 1 1 0 1 0 1 0.5 kHz 1 kHz 2 kHz 4 kHz .3-.2 Watch Timer Speed Selection Bits (fx = 4.19 MHz) 0 0 1 1 0 1 0 1 Set watch timer interrupt to 1s Set watch timer interrupt to 0.5s Set watch timer interrupt to 0.25s Set watch timer interrupt to 3.91ms .1 Watch Timer Enable Bit 0 1 Disable watch timer; Clear frequency dividing circuits Enable watch timer .0 Not used for S3C94A5/F94A5 4-39 S3C94A5/F94A5 INTERRUPT STRUCTURE 5 OVERVIEW INTERRUPT STRUCTURE The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H - 0001H. VECTOR SOURCES S1 0000H 0001H S2 S3 Sn NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The number of Sn value is expandable. Figure 5-1. S3C9-Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The systemlevel control points in the interrupt structure are therefore: -- Global interrupt enable and disable (by EI and DI instructions) -- Interrupt source enable and disable settings in the corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) The system mode register, SYM (DFH), is used to enable and disable interrupt processing. SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose. 5-1 INTERRUPT STRUCTURE S3C94A5/F94A5 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM88RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine. "EI" Instruction Execution nRESET Source Interrupts Source Interrupt Enable S R Q Interrupt Pending Register Interrpt priority is determind by software polling method Global Interrupt Control (EI, Di instruction) Vector Interrupt Cycle Figure 5-2. Interrupt Function Diagram 5-2 S3C94A5/F94A5 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. 2. 3. 4. A source generates an interrupt request by setting the interrupt request pending bit to "1". The CPU generates an interrupt acknowledge signal. The service routine starts and the source's pending flag is cleared to "0" by software. Interrupt priority must be determined by software polling method. INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced, the following conditions must be met: -- Interrupt processing must be enabled (EI, SYM.3 = "1") -- Interrupt must be enabled at the interrupt's source (peripheral control register) If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. 2. 3. 4. Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0") to disable all subsequent interrupts. Save the program counter and status flags to stack. Branch to the interrupt vector to fetch the service routine's address. Pass control to the interrupt service routine. When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence: 1. 2. 3. 4. 5. 6. Push the program counter's low-byte value to stack. Push the program counter's high-byte value to stack. Push the FLAGS register values to stack. Fetch the service routine's high-byte address from the vector address 0000H. Fetch the service routine's low-byte address from the vector address 0001H. Branch to the service routine specified by the 16-bit vector address. 5-3 INTERRUPT STRUCTURE S3C94A5/F94A5 S3C94A5/F94A5 INTERRUPT STRUCTURE The S3C94A5/F94A5 microcontroller has twenty three peripheral interrupt sources: -- Timer 0 match/capture interrupt -- Timer 0 overflow interrupt -- Timer 1 match/capture interrupt -- Timer 1 overflow interrupt -- Timer 2 match/capture interrupt -- Timer 2 overflow interrupt -- SIO interrupt -- Watch Timer interrupt -- Seven external interrupts for port 1 -- Six external interrupts for port 3 -- One external interrupt for port 4 -- One external interrupt for port 5 5-4 S3C94A5/F94A5 INTERRUPT STRUCTURE Vector Enable/Disable P1INT.0 Pending INTPND1.0 INTPND1.1 Sources P1.0 External Interript P1.1 External Interript P1.2 External Interript P1.3 External Interript P1.4 External Interript P1.5 External Interript P1.6 External Interript P3.0 External Interrupt P3.1 External Interrupt P3.2 External Interrupt P3.3 External Interrupt P3.4 External Interrupt P3.5 External Interrupt P4.7 External Interrupt P5.0 External Interript Timer 0 Match or Capture Timer 0 Overflow Timer 1 Match or Capture Timer 1 Overflow Timer 2 Match or Capture Timer 2 Overflow SIO Interrupt Watch Timer Interrupt P1INT.1 INTPND1.2 P1INT.2 INTPND1.3 P1INT.3 INTPND1.4 P1INT.4 INTPND1.5 P1INT.5 INTPND1.6 P1INT.6 0000H 0001H SYM.3 (EI, DI) INTPND2.0 P3INT.0 INTPND2.1 P3INT.1 INTPND2.2 P3INT.2 INTPND2.3 P3INT.3 INTPND2.4 P3ITN.4 INTPND2.5 P3INT.5 INTPND2.6 P4n5INT.4 INTPND2.7 P4n5INT.5 INTPND3.0 T0CON.1 INTPND3.1 T0CON.0 INTPND3.2 T1CON.1 INTPND3.3 T1CON.0 INTPND3.4 T2CON.1 INTPND3.5 T2CON.0 INTPND3.6 SIOCON.1 INTPND3.7 WTCON.6 Figure 5-3. S3C94A5/F94A5 Interrupt Structure 5-5 INTERRUPT STRUCTURE S3C94A5/F94A5 F Programming Tip -- How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD * * * INTPND1, #11111011B ; Clear P1.2's interrupt pending bit IRET 2. LD * * * INTPND3, #01111111B ; Clear watch timer interrupt pending bit IRET 5-6 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET 6 OVERVIEW SAM88RCRI INSTRUCTION SET The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8-bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces". ADDRESSING MODES There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes". 6-1 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR LD LDC LDE LDCD LDED LDCI LDEI POP PUSH dst dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst src Clear Load Load program memory Load external data memory Load program memory and decrement Load external data memory and decrement Load program memory and increment Load external data memory and increment Pop from stack Push to stack Arithmetic Instructions ADC ADD CP DEC INC SBC SUB dst,src dst,src dst,src dst dst dst,src dst,src Add with carry Add Compare Decrement Increment Subtract with carry Subtract Logic Instructions AND COM OR XOR dst,src dst dst,src dst,src Logical AND Complement Logical OR Logical exclusive OR 6-2 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions CALL IRET JP JP JR RET cc,dst dst cc,dst dst Call procedure Interrupt return Jump on condition code Jump unconditional Jump relative on condition code Return Bit Manipulation Instructions TCM TM dst,src dst,src Test complement under mask Test under mask Rotate and Shift Instructions RL RLC RR RRC SRA dst dst dst dst dst Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic CPU Control Instructions CCF DI EI IDLE NOP RCF SCF STOP Complement carry flag Disable interrupts Enable interrupts Enter Idle mode No operation Reset carry flag Set carry flag Enter Stop mode 6-3 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 - FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result. System Flags Register (FLAGS) D5H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Carry flag (C) Zero flag (Z) Sign flag (S) Overflow flag (V) Not mapped Figure 6-1. System Flags Register (FLAGS) FLAG DESCRIPTIONS Overflow Flag (FLAGS.4, V) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than - 128. It is also cleared to "0" following logic operations. Sign Flag (FLAGS.5, S) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. Zero Flag (FLAGS.6, Z) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. Carry Flag (FLAGS.7, C) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. 6-4 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag C Z S V 0 1 * - x Carry flag Zero flag Sign flag Overflow flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6-3. Instruction Set Symbols Symbol dst src @ PC FLAGS # H D B opc Destination operand Source operand Indirect register address prefix Program counter Flags register (D5H) Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode Description Description 6-5 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 Table 6-4. Instruction Notation Conventions Notation cc r rr R RR Ir IR Irr IRR X XS xl da ra im Condition code Working register only Working register pair Register or working register Register pair or working register pair Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed (short offset) addressing mode Indexed (long offset) addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Description Actual Operand Range See list of condition codes in Table 6-6. Rn (n = 0-15) RRp (p = 0, 2, 4, ..., 14) reg or Rn (reg = 0-255, n = 0-15) reg or RRp (reg = 0-254, even number only, where p = 0, 2, ..., 14) @Rn (n = 0-15) @Rn or @reg (reg = 0-255, n = 0-15) @RRp (p = 0, 2, ..., 14) @RRp or @reg (reg = 0-254, even only, where p = 0, 2, ..., 14) #reg[Rn] (reg = 0-255, n = 0-15) #addr[RRp] (addr = range -128 to +127, where p = 0, 2, ..., 14) #addr [RRp] (addr = range 0-8191, where p = 0, 2, ..., 14) addr (addr = range 0-8191) addr (addr = number in the range +127 to -128 that is an offset relative to the address of the next instruction) #data (data = 0-255) 6-6 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F CLR R1 RRC R1 SRA R1 RR R1 CLR IR1 RRC IR1 SRA IR1 RR IR1 LDCD r1,Irr2 RL R1 RL IR1 CP r1,r2 XOR r1,r2 CP r1,Ir2 XOR r1,Ir2 LDC r1,Irr2 LDC r2,Irr1 LDCI r1,Irr2 LD R2,R1 CALL IRR1 LD R2,IR1 LD IR2,R1 LD IR1,IM LD R1,IM CALL DA1 CP R2,R1 XOR R2,R1 CP IR2,R1 XOR IR2,R1 CP R1,IM XOR R1,IM POP R1 COM R1 PUSH R2 POP IR1 COM IR1 PUSH IR2 0 DEC R1 RLC R1 INC R1 JP IRR1 1 DEC IR1 RLC IR1 INC IR1 2 ADD r1,r2 ADC r1,r2 SUB r1,r2 SBC r1,r2 OR r1,r2 AND r1,r2 TCM r1,r2 TM r1,r2 3 ADD r1,Ir2 ADC r1,Ir2 SUB r1,Ir2 SBC r1,Ir2 OR r1,Ir2 AND r1,Ir2 TCM r1,Ir2 TM r1,Ir2 4 ADD R2,R1 ADC R2,R1 SUB R2,R1 SBC R2,R1 OR R2,R1 AND R2,R1 TCM R2,R1 TM R2,R1 5 ADD IR2,R1 ADC IR2,R1 SUB IR2,R1 SBC IR2,R1 OR IR2,R1 AND IR2,R1 TCM IR2,R1 TM IR2,R1 6 ADD R1,IM ADC R1,IM SUB R1,IM SBC R1,IM OR R1,IM AND R1,IM TCM R1,IM TM R1,IM LD r1, x, r2 LD r2, x, r1 LDC r1, Irr2, xL LDC r2, Irr2, xL LD r1, Ir2 LD Ir1, r2 LDC r1, Irr2, xs LDC r2, Irr1, xs 7 6-7 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) - U P P E R 0 1 2 3 4 5 N I B B L E 6 7 8 9 A B C H E X D E F LD r1,R2 LD r2,R1 JR cc,RA LD r1,IM JP cc,DA INC r1 IDLE STOP DI EI RET IRET RCF SCF CCF NOP 8 LD r1,R2 9 LD r2,R1 A B JR cc,RA C LD r1,IM D JP cc,DA E INC r1 F 6-8 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary 0000 1000 0111 (1) 1111 (1) 0110 (1) 1110 (1) 1101 0101 0100 1100 0110 (1) 1110 (1) 1001 0001 1010 0010 1111 (1) 0111 (1) 1011 0011 Mnemonic F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Description Always false Always true Carry No carry Zero Not zero Plus Minus Overflow No overflow Equal Not equal Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than Unsigned less than or equal - - C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S XOR V) = 0 (S XOR V) = 1 (Z OR (S XOR V)) = 0 (Z OR (S XOR V)) = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 Flags Set NOTES: 1. Indicate condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be us ed. 6-9 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: -- Instruction name (mnemonic) -- Full instruction name -- Source/destination format of the instruction operand -- Shorthand notation of the instruction's operation -- Textual description of the instruction's effect -- Specific flag settings affected by the instruction -- Detailed description of the instruction's format, execution time, and addressing mode(s) -- Programming example(s) explaining how to use the instruction 6-10 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET ADC -- Add With Carry ADC Operation: dst,src dst dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: C: Z: S: V: D: H: Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 12 13 Addr Mode dst src r r r lr Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. Always cleared to "0". Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. opc src dst 3 6 6 14 15 R R R IR opc dst src 3 6 16 R IM Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC ADC ADC ADC ADC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#11H R1 = 14H, R2 = 03H R1 = 1BH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 32H In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1. 6-11 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 ADD -- Add ADD Operation: dst,src dst dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: D: H: Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 02 03 Addr Mode dst src r r r lr Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. Always cleared to "0". Set if a carry from the low-order nibble occurred. opc src dst 3 6 6 04 05 R R R IR opc dst src 3 6 06 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD ADD ADD ADD ADD R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 15H, R2 = 03H R1 = 1CH, R2 = 03H Register 01H = 24H, register 02H = 03H Register 01H = 2BH, register 02H = 03H Register 01H = 46H In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1. 6-12 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET AND -- Logical AND AND Operation: dst,src dst dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 52 53 Addr Mode dst src r r r lr opc src dst 3 6 6 54 55 R R R IR opc dst src 3 6 56 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND AND AND AND AND R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#25H R1 = 02H, R2 = 03H R1 = 02H, R2 = 03H Register 01H = 01H, register 02H = 03H Register 01H = 00H, register 02H = 03H Register 01H = 21H In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1. 6-13 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 CALL -- Call Procedure CALL Operation: dst SP @SP SP @SP PC SP - 1 PCL SP -1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: Format: Bytes opc dst 3 Cycles 14 Opcode (Hex) F6 Addr Mode dst DA No flags are affected. opc dst 2 12 F4 IRR Examples: Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H: CALL 1521H SP = 0B0H (Memory locations 00H = 1AH, 01H = 4AH, where 4AH is the address that follows the instruction.) SP = 0B0H (00H = 1AH, 01H = 49H) CALL @RR0 In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 01H (because the two-byte instruction format was used). The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed. 6-14 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET CCF -- Complement Carry Flag CCF Operation: C NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) EF Example: Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one. 6-15 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 CLR -- Clear CLR Operation: dst dst "0" The destination location is cleared to "0". Flags: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) B0 B1 Addr Mode dst R IR No flags are affected. Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR CLR 00H @01H Register 00H = 00H Register 01H = 02H, register 02H = 00H In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 6-16 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET COM -- Complement COM Operation: dst dst NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 60 61 Addr Mode dst R IR Examples: Given: R1 = 07H and register 07H = 0F1H: COM COM R1 @R1 R1 = 0F8H R1 = 07H, register 07H = 0EH In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B). 6-17 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 CP -- Compare CP Operation: dst,src dst - src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: D: H: Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) A2 A3 Addr Mode dst src r r r lr Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. Unaffected. Unaffected. opc src dst 3 6 6 A4 A5 R R R IR opc dst src 3 6 A6 R IM Examples: 1. CP Given: R1 = 02H and R2 = 03H: R1,R2 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP JP INC LD R1,R2 UGE,SKIP R1 R3,R1 SKIP In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3. 6-18 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET DEC -- Decrement DEC Operation: dst dst dst - 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: D: H: Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 00 01 Addr Mode dst R IR Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is -128(80H) and result value is +127(7FH); cleared otherwise. Unaffected. Unaffected. Examples: Given: R1 = 03H and register 03H = 10H: DEC DEC R1 @R1 R1 = 02H Register 03H = 0FH In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH. 6-19 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 DI -- Disable Interrupts DI Operation: SYM (2) 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 8F No flags are affected. Example: Given: SYM = 04H: DI If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register and clears SYM.2 to "0", disabling interrupt processing. 6-20 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET EI -- Enable Interrupts EI Operation: SYM (2) 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 9F No flags are affected. Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt processing). 6-21 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 IDLE -- Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 6F Addr Mode dst src - - No flags are affected. Example: The instruction IDLE stops the CPU clock but not the system clock. 6-22 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET INC -- Increment INC Operation: dst dst dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: D: H: Format: Bytes dst | opc 1 Cycles 4 Opcode (Hex) rE r = 0 to F Addr Mode dst r Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is -128(80H); cleared otherwise. Unaffected. Unaffected. opc dst 2 4 4 20 21 R IR Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC INC INC R0 00H @R0 R0 = 1CH Register 00H = 0DH R0 = 1BH, register 01H = 10H In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. 6-23 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 IRET -- Interrupt Return IRET Operation: IRET FLAGS @SP SP SP + 1 PC @SP SP SP + 2 SYM(2) 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: Format: IRET (Normal) opc Bytes 1 Cycles 6 Opcode (Hex) BF All flags are restored to their original settings (that is, the settings before the interrupt occurred). 6-24 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET JP -- Jump JP JP Operation: cc,dst dst (Conditional) (Unconditional) If cc is true, PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: Format: (1) No flags are affected. Bytes (2) Cycles 8 (3) Opcode (Hex) ccD cc = 0 to F Addr Mode dst DA cc | opc dst 3 opc dst 2 8 30 IRR NOTES: 1. The 3-byte format is used for a conditional jump and the 2 -byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: JP JP C,LABEL_W @00H LABEL_W = 1000H, PC = 1000H PC = 0120H The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H. 6-25 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 JR -- Jump Relative JR Operation: cc,dst If cc is true, PC PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes). The range of the relative address is +127, -128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: Format: Bytes (1) No flags are affected. Cycles 6 (2) Opcode (Hex) ccB cc = 0 to F Addr Mode dst RA cc | opc dst 2 NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X PC = 1FF7H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 6-26 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET LD -- Load LD Operation: dst,src dst src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: Format: Bytes dst | opc src 2 Cycles 4 4 Opcode (Hex) rC r8 Addr Mode dst src r r IM R No flags are affected. src | opc dst 2 4 r9 r = 0 to F R r opc dst | src 2 4 4 C7 D7 r Ir lr r opc src dst 3 6 6 E4 E5 R R R IR opc dst src 3 6 6 E6 D6 R IR IM IM opc src dst 3 6 F5 IR R opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r 6-27 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 LD -- Load LD Examples: (Continued) Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD R0,#10H R0,01H 01H,R0 R1,@R0 @R0,R1 00H,01H 02H,@00H 00H,#0AH @00H,#10H @00H,02H R0,#LOOP[R1] #LOOP[R0],R1 R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 00H = 20H, register 01H = 20H Register 02H = 20H, register 00H = 01H Register 00H = 0AH Register 00H = 01H, register 01H = 10H Register 00H = 01H, register 01H = 02, register 02H = 02H R0 = 0FFH, R1 = 0AH Register 31H = 0AH, R0 = 01H, R1 = 0AH 6-28 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET LDC/LDE -- Load Memory LDC/LDE Operation: dst,src dst src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory. Flags: Format: Bytes 1. 2. 3. opc opc opc dst | src src | dst dst | src XS 2 2 3 Cycles 10 10 12 Opcode (Hex) C3 D3 E7 Addr Mode dst src r Irr r Irr r XS [rr] No flags are affected. 4. opc src | dst XS 3 12 F7 XS [rr] r 5. opc dst | src XLL XLH 4 14 A7 r XL [rr] 6. opc src | dst XLL XLH 4 14 B7 XL [rr] r 7. opc dst | 0000 DAL DAH 4 14 A7 r DA 8. opc src | 0000 DAL DAH 4 14 B7 DA r 9. opc dst | 0001 DAL DAH 4 14 A7 r DA 10. opc src | 0001 DAL DAH 4 14 B7 DA r NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0 -1. 2. For formats 3 and 4, the destination addres s 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory. 6-29 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 LDC/LDE -- Load Memory LDC/LDE Examples: (Continued) Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC LDE LDC * R0,@RR2 R0,@RR2 @RR2,R0 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; R0 contents of program memory location 0104H R0 = 1AH, R2 = 01H, R3 = 04H R0 contents of external data memory location 0104H R0 = 2AH, R2 = 01H, R3 = 04H 11H (contents of R0) is loaded into program memory location 0104H (RR2), working registers R0, R2, R3 AE no change 11H (contents of R0) is loaded into external data memory location 0104H (RR2), working registers R0, R2, R3 AE no change R0 contents of program memory location 0061H (01H + RR4), R0 = AAH, R2 = 00H, R3 = 60H R0 contents of external data memory location 0061H (01H + RR4), R0 = BBH, R4 = 00H, R5 = 60H 11H (contents of R0) is loaded into program memory location 0061H (01H + 0060H) 11H (contents of R0) is loaded into external data memory location 0061H (01H + 0060H) R0 contents of program memory location 1104H (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H R0 contents of external data memory location 1104H (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H R0 contents of program memory location 1104H, R0 = 88H R0 contents of external data memory location 1104H, R0 = 98H 11H (contents of R0) is loaded into program memory location 1105H, (1105H) 11H 11H (contents of R0) is loaded into external data memory location 1105H, (1105H) 11H LDE @RR2,R0 LDC R0,#01H[RR4] LDE LDC (note) LDE LDC LDE LDC LDE LDC (note) LDE R0,#01H[RR4] #01H[RR4],R0 #01H[RR4],R0 R0,#1000H[RR2] R0,#1000H[RR2] R0,1104H R0,1104H 1105H,R0 1105H,R0 NOTE: These instructions are not supported by masked ROM type devices. 6-30 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET LDCD/LDED -- Load Memory and Decrement LDCD/LDED Operation: dst,src dst src rr rr - 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes `Irr' an even number for program memory and an odd number for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E2 Addr Mode dst src r Irr No flags are affected. Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; ; ; ; ; ; 0CDH (contents of program memory location 1033H) is loaded into R8 and RR6 is decremented by one R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 RR6 - 1) 0DDH (contents of data memory location 1033H) is loaded into R8 and RR6 is decremented by one (RR6 RR6 - 1) R8 = 0DDH, R6 = 10H, R7 = 32H LDED R8,@RR6 6-31 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 LDCI/LDEI -- Load Memory and Increment LDCI/LDEI Operation: dst,src dst src rr rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory. Flags: Format: Bytes opc dst | src 2 Cycles 10 Opcode (Hex) E3 Addr Mode dst src r Irr No flags are affected. Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; ; ; ; ; ; 0CDH (contents of program memory location 1033H) is loaded into R8 and RR6 is incremented by one (RR6 RR6 + 1) R8 = 0CDH, R6 = 10H, R7 = 34H 0DDH (contents of data memory location 1033H) is loaded into R8 and RR6 is incremented by one (RR6 RR6 + 1) R8 = 0DDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 6-32 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET NOP -- No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. No flags are affected. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) FF Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time. 6-33 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 OR -- Logical OR OR Operation: dst,src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 42 43 Addr Mode dst src r r r lr opc src dst 3 6 6 44 45 R R R IR opc dst src 3 6 46 R IM Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR OR OR OR OR R0,R1 R0,@R2 00H,01H 01H,@00H 00H,#02H R0 = 3FH, R1 = 2AH R0 = 37H, R2 = 01H, register 01H = 37H Register 00H = 3FH, register 01H = 37H Register 00H = 08H, register 01H = 0BFH Register 00H = 0AH In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats. 6-34 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET POP -- Pop From Stack POP Operation: dst dst @SP SP SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: Format: Bytes opc dst 2 Cycles 8 8 Opcode (Hex) 50 51 Addr Mode dst R IR No flags affected. Examples: Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH = 55H: POP POP 00H @00H Register 00H = 55H, SP = 0BCH Register 00H = 01H, register 01H = 55H, SP = 0BCH In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 0BBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH. 6-35 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 PUSH -- Push To Stack PUSH Operation: src SP SP - 1 @SP src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: Format: Bytes opc src 2 Cycles 8 8 Opcode (Hex) 70 71 Addr Mode dst R IR No flags are affected. Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H: PUSH PUSH 40H @40H Register 40H = 4FH, stack register 0BFH = 4FH, SP = 0BFH Register 40H = 4FH, register 4FH = 0AAH, stack register 0BFH = 0AAH, SP = 0BFH In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP points to location 0BFH. 6-36 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET RCF -- Reset Carry Flag RCF Operation: RCF C0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) CF Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero. 6-37 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 RET-- Return RET Operation: PC @SP SP SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: Format: Bytes opc 1 Cycles 8 Opcode (Hex) AF No flags are affected. Example: Given: SP = 0BCH, (SP) = 101AH, and PC = 1234: RET PC = 101AH, SP = 0BEH The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 0BEH. 6-38 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET RL -- Rotate Left RL Operation: dst C dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 C 0 Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 90 91 Addr Mode dst R IR Examples: Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL RL 00H @01H Register 00H = 55H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags. 6-39 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 RLC -- Rotate Left Through Carry RLC Operation: dst dst (0) C C dst (7) dst (n + 1) dst (n), n = 0-6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 C 0 Flags: C: Z: S: V: D: H: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) 10 11 Addr Mode dst R IR Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC RLC 00H @01H Register 00H = 54H, C = "1" Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag. 6-40 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET RR -- Rotate Right RR Operation: dst C dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 C 0 Flags: C: Z: S: V: D: H: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) E0 E1 Addr Mode dst R IR Examples: Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR RR 00H @01H Register 00H = 98H, C = "1" Register 01H = 02H, register 02H = 8BH, C = "1" In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1". 6-41 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 RRC -- Rotate Right Through Carry RRC Operation: dst dst (7) C C dst (0) dst (n) dst (n + 1), n = 0-6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 C 0 Flags: C: Z: S: V: D: H: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0" cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) C0 C1 Addr Mode dst R IR Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC RRC 00H @01H Register 00H = 2AH, C = "1" Register 01H = 02H, register 02H = 0BH, C = "1" In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0". 6-42 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET SBC -- Subtract With Carry SBC Operation: dst,src dst dst - src - c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: C: Z: S: V: D: H: Set if a borrow occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign if the result is the same as the sign of the source; cleared otherwise. Always set to "1". Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 32 33 Addr Mode dst src r r r lr opc src dst 3 6 6 34 35 R R R IR opc dst src 3 6 36 R IM Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC SBC SBC SBC SBC R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#8AH R1 = 0CH, R2 = 03H R1 = 05H, R2 = 03H, register 03H = 0AH Register 01H = 1CH, register 02H = 03H Register 01H = 15H,register 02H = 03H, register 03H = 0AH Register 01H = 95H; C, S, and V = "1" In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1. 6-43 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 SCF -- Set Carry Flag SCF Operation: C1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes opc 1 Cycles 4 Opcode (Hex) DF Example: The statement SCF sets the carry flag to logic one. 6-44 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET SRA -- Shift Right Arithmetic SRA Operation: dst dst (7) dst (7) C dst (0) dst (n) dst (n + 1), n = 0-6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 C 6 0 Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1". Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst 2 Cycles 4 4 Opcode (Hex) D0 D1 Addr Mode dst R IR Examples: Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA SRA 00H @02H Register 00H = 0CD, C = "0" Register 02H = 03H, register 03H = 0DEH, C = "0" In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H. 6-45 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 STOP -- Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. Flags: Format: Bytes opc 1 Cycles 4 Opcode (Hex) 7F Addr Mode dst src - - No flags are affected. Example: The statement STOP halts all microcontroller operations. 6-46 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET SUB -- Subtract SUB Operation: dst,src dst dst - src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: D: H: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. Always set to "1". Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 22 23 Addr Mode dst src r r r lr opc src dst 3 6 6 24 25 R R R IR opc dst src 3 6 26 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB SUB SUB SUB SUB SUB R1,R2 R1,@R2 01H,02H 01H,@02H 01H,#90H 01H,#65H R1 = 0FH, R2 = 03H R1 = 08H, R2 = 03H Register 01H = 1EH, register 02H = 03H Register 01H = 17H, register 02H = 03H Register 01H = 91H; C, S, and V = "1" Register 01H = 0BCH; C and S = "1", V = "0" In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1. 6-47 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 TCM -- Test Complement Under Mask TCM Operation: dst,src (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always cleared to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 62 63 Addr Mode dst src r r r lr opc src dst 3 6 6 64 65 R R R IR opc dst src 3 6 66 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM TCM TCM TCM TCM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#34 R0 = 0C7H, R1 = 02H, Z = "1" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "1" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" Register 00H = 2BH, Z = "0" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation. 6-48 S3C94A5/F94A5 SAM88RCRI INSTRUCTION SET TM -- Test Under Mask TM Operation: dst,src dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) 72 73 Addr Mode dst src r r r lr opc src dst 3 6 6 74 75 R R R IR opc dst src 3 6 76 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM TM TM TM TM R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C7H, R1 = 02H, Z = "0" R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, register 01H = 02H, Z = "0" Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" Register 00H = 2BH, Z = "1" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation. 6-49 SAM88RCRI INSTRUCTION SET S3C94A5/F94A5 XOR -- Logical Exclusive OR XOR Operation: dst,src dst dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected. Format: Bytes opc dst | src 2 Cycles 4 6 Opcode (Hex) B2 B3 Addr Mode dst src r r r lr opc src dst 3 6 6 B4 B5 R R R IR opc dst src 3 6 B6 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR XOR XOR XOR XOR R0,R1 R0,@R1 00H,01H 00H,@01H 00H,#54H R0 = 0C5H, R1 = 02H R0 = 0E4H, R1 = 02H, register 02H = 23H Register 00H = 29H, register 01H = 02H Register 00H = 08H, register 01H = 02H, register 02H = 23H Register 00H = 7FH In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0. 6-50 S3C94A5/F94A5 CLOCK CIRCUITS 7 OVERVIEW CLOCK CIRCUITS The S3C94A5/F94A5 has the oscillator circuit for system clock. There are three methods being oscillation. First, A method that a crystal, ceramic, or resistor is connected between XIN and XOUT. Second, the name is external RC oscillator; A resistor is connected between XIN and VDD. Third, the name is internal RC oscillator; XIN and XOUT have to be disconnected. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: -- Crystal, ceramic resonator, RC oscillation source (main clock only), or an external clock -- Internal or external RC oscillation source -- Oscillator stop and wake-up functions -- Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) -- Clock circuit control register, CLKCON -- STOP control register, STPCON CPU CLOCK NOTATION In this document, the following notation is used for descriptions of the CPU clock; fx: main clock fxt: sub clock (the fxt is not implemented in the S3C94A5/F94A5) fxx: selected system clock 7-1 CLOCK CIRCUITS S3C94A5/F94A5 MAIN OSCILLATOR CIRCUITS VDD R XIN XIN XOUT NC XOUT Figure 7-1. Crystal/Ceramic Oscillator(fx) Figure 7-4. External RC Oscillator(fx) XIN NC XIN XOUT NC XOUT Figure 7-2. External Oscillator(fx) Figure 7-5. Internal RC Oscillator(fx) XIN R XOUT Figure 7-3. RC Oscillator(fx) 7-2 S3C94A5/F94A5 CLOCK CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: -- In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation or an external interrupt. (with RC delay noise filter) -- In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer counters and watch timer. Idle mode is released by a reset or by an external or internal interrupts. Stop Release INT Main-System Oscillator Circuit fX fXT Sub-system Oscillator Circuit Selector 1 fXX Stop Logic "0" Stop Logic "0" STOP OSC inst. STPCON 1/1 1/8-1/4096 Frequency Dividing Circuit 1/2 1/8 1/16 Basic Timer Timer/Counters Watch Timer SIO A/D Converter Logic "1" CLKCON.4-.3 Selector 2 CPU IDLE Instruction NOTE: The fxt is not implemented in the S3C94A5/F94A5. Figure 7-6. System Clock Circuit Diagram 7-3 CLOCK CIRCUITS S3C94A5/F94A5 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: -- Oscillator IRQ wake-up function enable/disable -- Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release (This is called the "IRQ wake-up" function). The IRQ "wake-up" enable bit is CLKCON.7. After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fx, fx/2, or fx/8 by setting the CLKCON. System Clock Control Register (CLKCON) D4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Oscillator IRQ wake-up function bit: 0 = Enable IRQ for main wake-up in power down mode 1 = Disable IRQ for main wake-up in power down mode Not used for S3C94A5/F94A5 (must keep always "0") Divide-by selection bits for CPU clock frequency: 00 = fxx/16 01 = fxx/8 10 = fXx/2 11 = fxx Not used for S3C94A5/F94A5 (must keep always "0") Figure 7-7. System Clock Control Register (CLKCON) 7-4 S3C94A5/F94A5 CLOCK CIRCUITS STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: -- Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B". Stop Control Register (STPCON) E0H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB STOP control bits: 10100101 = Enable STOP instruction Other values = Disable STOP instruction Figure 7-8. STOP Control Register (STPCON) F PROGRAMMING TIP -- How to Use Stop Instruction This example shows how to go STOP mode when a main clock is selected as the system clock. LD STOP NOP NOP NOP LD STPCON,#10100101B ; Enable STOP instruction ; Enter STOP mode STPCON,#00000000B ; Release STOP mode ; Disable STOP instruction 7-5 S3C94A5/F94A5 RESET and POWER-DOWN 8 OVERVIEW RESET and POWER-DOWN SYSTEM RESET During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C94A5/F94A5 into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both VDD and nRESET are High level), the nRESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values (see Table 8-1). In summary, the following sequence of events occurs during a reset operation: -- All interrupts are disabled. -- The watchdog function (basic timer) is enabled. -- Port1-5 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits. -- Peripheral control and data registers are disabled and reset to their default hardware values. -- The program counter (PC) is loaded with the program reset address in the ROM, 0100H. -- When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed. NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON. 8-1 RESET and POWER-DOWN S3C94A5/F94A5 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 2A. All system functions stop when the clock "freezes", but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by external interrupts. Example: LD STOP NOP NOP NOP LD STPCON,#10100101B STPCON,#00000000B NOTES 1. 2. Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage. In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus. To enable/disable STOP instruction, the STPCON register should be written with 10100101B/other values before/after stop instruction. 3. Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal goes active (Low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H. Using an External Interrupt to Release Stop Mode External interrupts can be used to release stop mode. For the S3C94A5 microcontroller, we recommend using the INT interrupt, P1, P3, P4.7, and P5.0. 8-2 S3C94A5/F94A5 RESET and POWER-DOWN IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active: -- Interrupt logic -- Basic timer -- Timers -- Watch timer I/O port pins retain the mode (input or output) they had at the time Idle mode was entered. Idle Mode Release You can release Idle mode in one of two ways: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware reset value for the CLKCON register. If interrupts are masked, a reset is the only way to release idle mode. Activate any enabled interrupt causing idle mode to be released. When you use an interrupt to release Idle mode, the 2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately following the one which initiated Idle mode is executed. 2. 8-3 RESET and POWER-DOWN S3C94A5/F94A5 HARDWARE RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: -- A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively. -- An 'x' means that the bit value is undefined following RESET. -- A dash ('-') means that the bit is either not used or not mapped. Table 8-1. Register Values after RESET Register Name Mnemonic Address Dec Hex 7 6 Bit Values after RESET 5 4 3 2 1 0 Locations B0H -- B3H are not mapped Timer 0 control register Timer 0 data register (high byte) Timer 0 data register (low byte) Timer 0 counter (high byte) Timer 0 counter (low byte) Timer 1 control resistor Timer 1 data register (high byte) Timer 1 data register (low byte) Timer 1 counter (high byte) Timer 1 counter (low byte) Timer 2 control register Timer 2 data register Timer 2 counter A/D converter control register A/D converter data register (high byte) A/D converter data register (low byte) System clock control register System flags register Interrupt pending register 1 Interrupt pending register 2 Interrupt pending register 3 Stack pointer Watch timer control register T0CON T0DATAH T0DATAL T0CNTH T0CNTL T1CON T1DATAH T1DATAL T1CNTH T1CNTL T2CON T2DATA T2CNT ADCON ADDATAH ADDATAL CLKCON FLAGS INTPND1 INTPND2 INTPND3 SP WTCON 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X - 0 X - 0 0 X - 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X - 0 X 0 0 0 X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X - 0 X 0 0 0 X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X - 0 X 0 0 0 X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X - 0 - 0 0 0 X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X - 0 - 0 0 0 X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X X 0 - 0 0 0 X 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 X X 0 - 0 0 0 X - Locations DBH is not mapped 8-4 S3C94A5/F94A5 RESET and POWER-DOWN Table 8-1. Register Values after RESET (Continued) Register Name Mnemonic Address Dec Basic timer control register Basic timer counter BTCON BTCNT 220 221 Hex DCH DDH 7 0 0 6 0 0 Bit Values after RESET 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 0 0 Location DEH is not mapped System mode register STOP control register SIO control register SIO data register SIO prescaler register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register SYM STPCON SIOCON SIODATA SIOPS P1 P2 P3 P4 P5 223 224 225 226 227 228 229 230 231 232 DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H - 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 Location E9H is not mapped Port 1 control register (high byte) Port 1 control register (low byte) Port 1 interrupt control register Port 1 interrupt edge selection register (high byte) Port 1 interrupt edge selection register (low byte) Port 2 control register (high byte) Port 2 control register (low byte) Port 2 pull-up control register Port 3 control register (high byte) Port 3 control register (low byte) Port 3 pull-up control register Port 3 interrupt control register Port 3 interrupt edge selection register (high byte) Port 3 interrupt edge selection register (low byte) Port 4 control register (high byte) Port 4 control register (middle byte) P1CONH P1CONL P1INT P1EDGEH P1EDGEL P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P3INT P3EDGEH P3EDGEL P4CONH P4CONM 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H - 0 - - 0 - 0 - - 0 - - - 0 - 0 - 0 0 - 0 - 0 - 0 0 - - - 0 - 0 0 0 0 0 0 - 0 0 0 0 0 0 - 0 - 0 0 0 0 0 0 - 0 0 0 0 0 0 - 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8-5 RESET and POWER-DOWN S3C94A5/F94A5 Table 8-1. Register Values after RESET (Continued) Register Name Mnemonic Address Dec Port 4 control register (low byte) Port 4 and 5 interrupt control register Port 4 pull-up control register Port 5 control register (high byte) Port 5 control register (low byte) P4CONL P4n5INT P4PUR P5CONH P5CONL 250 251 252 253 254 Hex FAH FBH FCH FDH FEH 7 - - 0 0 - 6 - - 0 0 0 Bit Values after RESET 5 0 0 0 0 0 4 0 0 0 0 0 3 0 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Location FFH is not mapped. 8-6 S3C94A5/F94A5 I/O PORTS 9 OVERVIEW Port 1 I/O PORTS The S3C94A5/F94A5 microcontroller has five bit-programmable I/O ports, P1-P5. Port 1 and port 5 are 7-bit ports, port 2 and port 3 are 6-bit ports and port 4 is 8-bit ports. This gives a total of 34 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C94A5/F94A5 can be configured to input or output mode. Table 9-1 gives you a general overview of S3C94A5/F94A5 I/O port functions. Table 9-1. S3C94A5 Port Configuration Overview Configuration Options 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P1 can be used as input for external interrupts INT. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P2 can be used as AD0-AD5. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P3 can be used as input for external interrupts INT and can be used as AD6-AD11, and can be used as CLO, BUZ, T0OUT, T0CAP, and T0CLK. 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. Alternatively P4 can be used as AD12-AD14 and can be used as SCK, SI, SO, T2CAP, T1CAP, T2OUT, and T1OUT and P4.7 can be used as input for external interrupts INT. 1-bit programmable I/O port. Input or push-pull, open-drain output and software assignable pull-ups. Alternatively P5.0 can be used as input for external interrupts INT and can be used as AD15. 2 3 4 5 9-1 I/O PORTS S3C94A5/F94A5 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all five S3C94A5/F94A5 I/O port data registers. Data registers for ports 1, 2, 3, 4, and 5 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Mnemonic P1 P2 P3 P4 P5 Decimal 228 229 230 231 232 Hex E4H E5H E6H E7H E8H R/W R/W R/W R/W R/W R/W S3C94A5/F94A5 I/O Port Data Register Format (n = 1-5) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0 Figure 9-1. S3C94A5/F94A5 I/O Port Data Register Format 9-2 S3C94A5/F94A5 I/O PORTS PORT 1 Port 1 is a 7-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E4H in page 0. P1.0-P1.6 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P1.0-P1.3): INT -- High-nibble pins (P1.4-P1.6): INT Port 1 Control Registers (P1CONH, P1CONL) Port 1 has two 8-bit control registers: P1CONH for P1.4-P1.6 and P1CONL for P1.0-P1.3. A reset clears the P1CONH and P1CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input (with or without pull-up) or output mode (push-pull or open-drain). When programming this port, please remember that any alternative peripheral I/O function you configure using the port 1 control register must also be enabled in the associated peripheral module. Port 1 Interrupt Enable, Pending, and Edge Selection Registers (P1INT, INTPND1, P1EDGEH/P1EDGEL) To process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register P1INT (ECH, page 0), the port 1 interrupt pending bits INTPND1 (D6H, page 0), and the port 1 interrupt edge selection register P1EDGEH (EDH, page 0) and P1EDGEL (EEH, page 0). The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1 register at regular intervals. When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit. 9-3 I/O PORTS S3C94A5/F94A5 Port 1 Control Register, High Byte (P1CONH) EAH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P1.6 (INT) P1.5 (INT) P1.4 (INT) P1CONH bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Schmitt trigger input mode with pull-up Figure 9-2. Port 1 Control Register, High Byte (P1CONH) Port 1 Control Register, Low Byte (P1CONL) EBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 (INT) P1.2 (INT) P1.1 (INT) P1.0 (INT) P1CONL bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Schmitt trigger input mode with pull-up Figure 9-3. Port 1 Control Register, Low Byte (P1CONL) 9-4 S3C94A5/F94A5 I/O PORTS Port 1 Interrupt Control Register (P1INT) ECH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) P1INT bit configuration settings: 0 1 Disable interrupt Enable interrupt Figure 9-4. Port 1 Interrupt Control Register (P1INT) Interrupt Pending Register 1 (INTPND1) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 used (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND1 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-5. Interrupt Pending Register 1 (INTPND1) 9-5 I/O PORTS S3C94A5/F94A5 Port 1 Interrupt Edge Selection Register, High Byte (P1EDGEH) EDH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P1.6 (INT) P1.5 (INT) P1.4 (INT) P1EDGEH bit-pair configuration settings: 00 01 10 11 Falling edge detection Rising edge detection Both rising and falling edges detection Not available Figure 9-6. Port 1 Interrupt Edge Selection Register, High Byte (P1EDGEH) Port 1 Interrupt Edge Selection Register, Low Byte (P1EDGEL) EEH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 (INT) P1.2 (INT) P1.1 (INT) P1.0 (INT) P1EDGEL bit-pair configuration settings: 00 01 10 11 Falling edge detection Rising edge detection Both rising and falling edges detection Not available Figure 9-7. Port 1 Interrupt Edge Selection Register, Low Byte (P1EDGEL) 9-6 S3C94A5/F94A5 I/O PORTS PORT 2 Port 2 is a 6-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E5H in page 0. P2.0-P2.5 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P2.0-P2.3): AD0-AD3 -- High-nibble pins (P2.4-P2.5): AD4-AD5 Port 2 Control Registers (P2CONH, P2CONL) Port 2 has two 8-bit control registers: P2CONH for P2.4-P2.5 and P2CONL for P2.0-P2.3. A reset clears the P2CONH and P2CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 2 control register must also be enabled in the associated peripheral module. Port 2 Pull-up Resistor Control Register (P2PUR) Using the port 2 pull-up control register, P2PUR (F1H, page 0), you can configure pull-up resistors to individual port 2 pins. Port 2 Control Register, High Byte (P2CONH) EFH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P2.5/AD5 P2.4/AD4 P2CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD4, AD5) Figure 9-8. Port 2 Control Register, High Byte (P2CONH) 9-7 I/O PORTS S3C94A5/F94A5 Port 2 Control Register, Low Byte (P2CONL) F0H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P2.3/AD3 P2.2/AD2 P2.1/AD1 P2.0/AD0 P2CONL bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD0, AD1, AD2, AD3) Figure 9-9. Port 2 Control Register, Low Byte (P2CONL) Port 2 Pull-up Control Register (P2PUR) F1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P2PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor NOTE: A pull-up resistor of port 2 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-10. Port 2 Pull-up Control Register (P2PUR) 9-8 S3C94A5/F94A5 I/O PORTS PORT 3 Port 3 is a 6-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E6H in page 0. P3.0-P3.5 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P3.0-P3.3): AD6-AD9, CLO, BUZ, T0OUT/T0PWM, INT -- High-nibble pins (P3.4-P3.5): AD10-AD11, T0CAP, T0CLK, INT Port 3 Control Registers (P3CONH, P3CONL) Port 3 has two 8-bit control registers: P3CONH for P3.3-P3.5 and P3CONL for P3.0-P3.2. A reset clears the P3CONH and P3CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 3 control register must also be enabled in the associated peripheral module. Port 3 Pull-up Resistor Control Register (P3PUR) Using the port 3 pull-up control register, P3PUR (F4H, page 0), you can configure pull-up resistors to individually port 3 pins. Port 3 Interrupt Enable, Pending, and Edge Selection Registers(P3INT, INTPND2.5-0, P3EDGEH/P3EDGEL) To process external interrupts at the port 3 pins, three additional control registers are provided: the port 3 interrupt enable register P3INT (F5H, page 0), the port 3 interrupt pending bits INTPND2.5-.0 (D7H, page 0), and the port 3 interrupt edge selection register P3EDGEH (F6H, page 0) and P3EDGEL (F7H, page 0). The port 3 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND2.5-.0 register at regular intervals. When the interrupt enable bit of any port 3 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND2 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND2 bit. 9-9 I/O PORTS S3C94A5/F94A5 Port 3 Control Register, High Byte (P3CONH) F2H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P3.5/AD11/ T0CLK (INT) P3.4/AD10/ T0CAP (INT) P3.3/AD9/ T0OUT/P0PWM (INT) P3CONH.6-.5 and P3CONH.4-.3 bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (T0CAP, T0CLK) Push-pull output mode N-channel open-drain output mode Alternative function (AD10, AD11) P3CONH.2-.0 bits pin configuration settings: 000 001 010 011 100 Other Values Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD9) Alternative function (T0OUT/T0PWM) Not avaliable Figure 9-11. Port 3 Control Register, High Byte (P3CONH) 9-10 S3C94A5/F94A5 I/O PORTS Port 3 Control Register, Low Byte (P3CONL) F3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.2/AD8 (INT) P3.1/AD7/BUZ (INT) P3.0/AD6/CLO (INT) P3CONL.7-.6 bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD8) P3CONL.5-.3 and P3CONL.2-.0 bits pin configuration settings: 000 001 010 011 100 Other Values Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Alternative function (AD6, AD7) Alternative function (CLO, BUZ) Not available NOTE: CLO is CPU clock output. Figure 9-12. Port 3 Control Register, Low Byte (P3CONL) 9-11 I/O PORTS S3C94A5/F94A5 Port 3 Interrupt Control Register (P3INT) F5H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 (INT) (INT) (INT) (INT) (INT) (INT) P3INT bit configuration settings: 0 1 Disable interrupt Enable interrupt Figure 9-13. Port 3 Interrupt Control Register (P3INT) Interrupt Pending Register 2 (INTPND2) D7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P5.0 P4.7 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND2 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-14. Interrupt Pending Register 2 (INTPND2) 9-12 S3C94A5/F94A5 I/O PORTS Port 3 Interrupt Edge Selection Register, High Byte (P3EDGEH) F6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P3.5 (INT) P3.4 (INT) P3EDGEH bit-pair configuration settings: 00 01 10 11 Falling edge detection Rising edge detection Both rising and falling edges detection Not available Figure 9-15. Port 3 Interrupt Edge Selection Register, High Byte (P3EDGEH) Port 3 Interrupt Edge Selection Register, Low Byte (P3EDGEL) F7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.3 (INT) P3.2 (INT) P3.1 (INT) P3.0 (INT) P3EDGEL bit-pair configuration settings: 00 01 10 11 Falling edge detection Rising edge detection Both rising and falling edges detection Not available Figure 9-16. Port 3 Interrupt Edge Selection Register, Low Byte (P3EDGEL) 9-13 I/O PORTS S3C94A5/F94A5 Port 3 Pull-up Control Register (P3PUR) F4H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 P3PUR bit pin configuration settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor A pull-up resistor of port 3 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-17. Port 3 Pull-up Control Register (P3PUR) 9-14 S3C94A5/F94A5 I/O PORTS PORT 4 Port 4 is a 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E7H in page 0. P4.0-P4.7 can serve as inputs (with or without pull-up), as outputs (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P4.0-P4.3): AD12-AD13, T1OUT/T1PWM, T2OUT/T2PWM, T1CAP, T2CAP -- High-nibble pins (P4.4-P4.7): SO, SI, SCK, AD14, INT Port 4 Control Registers (P4CONH, P4CONM and P4CONL) Port 4 has three 8-bit control registers: P4CONH for P4.6-P4.7, P4CONM for P4.2-P4.5, and P4CONL for P4.0- P4.1. A reset clears the P4CONH, P4CONM and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 4 control register must also be enabled in the associated peripheral module. Port 4 Pull-up Resistor Control Register (P4PUR) Using the port 4 pull-up control register, P4PUR (FCH, page 0), you can configure pull-up resistors to individually port 4 pins. Port 4.7 Interrupt Enable, Pending, and Edge Selection Registers (P4n5INT.4, INTPND2.6, P4n5INT.1-.0) To process external interrupt at the port 4.7 pin, two additional control registers are provided: the port 4.7 interrupt enable register P4n5INT.4 (FBH, page 0), the port 4.7 interrupt pending bit INTPND2.6 (D7H, page 0), and the port 4.7 interrupt edge selection register P4n5INT.1-.0 (FBH, page 0). The port 4.7 interrupt pending register bit lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND2.6 register at regular intervals. When the interrupt enable bit of port 4.7 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND2 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND2 bit. 9-15 I/O PORTS S3C94A5/F94A5 Port 4 Control Register, High Byte (P4CONH) F8H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P4.7/AD14 (INT) P4.6/SCK P4CONH bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (SCK) Push-pull output mode N-channel open-drain output mode Alternative function (SCK, AD14) Figure 9-18. Port 4 Control Register, High Byte (P4CONH) Port 4 Control Register, Middle Byte (P4CONM) F9H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P4.5/SI P4.4/SO P4.3/T2CAP P4.2/T1CAP P4CONM bit-pair pin configuration settings: 00 01 10 11 Schmitt trigger input mode (T1CAP, T2CAP, SI) Push-pull output mode N-channel open-drain output mode Alternative function (SO) Figure 9-19. Port 4 Control Register, Middle Byte (P4CONM) 9-16 S3C94A5/F94A5 I/O PORTS Port 4 Control Register, Low Byte (P4CONL) FAH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P4.1/AD13/ T2OUT/T2PWM P4.0/AD12/ T1OUT/T1PWM P4CONL bits pin configuration settings: 000 001 010 011 100 Other Values Schmitt trigger input mode Push-pull output mode N-channel open-drain output mode Alternative function (T1OUT/T1PWM, T2OUT/T2PWM) Alternative function (AD12-AD13) Not available Figure 9-20. Port 4 Control Register, Low Byte (P4CONL) Port 4 Pull-up Control Register (P4PUR) FCH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P4PUR bit configuration settings: 0 1 NOTE: Disable pull-up resistor Enable pull-up resistor A pull-up resistor of port 4 is automatically disabled when the corresponding pin is selected as push-pull output or alternative function. Figure 9-21. Port 4 Pull-up Control Register (P4PUR) 9-17 I/O PORTS S3C94A5/F94A5 Port 4 and 5 Interrupt Control Register (P4n5INT) FBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P5.0 P4.7 (INT) (INT) P5.0 (INT) P4.7 (INT) P4n5INT.5 and P4n5INT.4 bit configuration settings: 0 1 Disable interrupt Enable interrupt P4n5INT.3-.2 and P4n5INT.1-.0 bit-pair configuration settings: 00 01 10 11 Falling edge detection Rising edge detection Both rising and falling edges detection Not available Figure 9-22. Port 4 and 5 Interrupt Control Register (P4n5INT) Interrupt Pending Register 2 (INTPND2) D7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P5.0 P4.7 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND2 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-23. Interrupt Pending Register 2 (INTPND2) 9-18 S3C94A5/F94A5 I/O PORTS PORT 5 Port 5 is a 7-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E8H in page 0. P5.0-P5.6 can serve as inputs (with or without pull-up) as output (push-pull or open-drain) or you can be configured the following functions. -- Low-nibble pins (P5.0-P5.3): AD15 and INT for only P5.0 Port 5 Control Registers (P5CONH, P5CONL) Port 5 has two 8-bit control registers: P5CONH for P5.3-P5.6 and P4CONL for P5.0-P5.2. A reset clears the P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input (with or without pull-up) or output mode (push-pull or open-drain) and enable the alternative functions. When programming this port, please remember that any alternative peripheral I/O function you configure using the port 5 control register must also be enabled in the associated peripheral module. Port 5.0 Interrupt Enable, Pending, and Edge Selection Registers (P4n5INT.5, INTPND2.7, P4n5INT.3-.2) To process external interrupt at the port 5.0 pin, two additional control registers are provided: the port 5.0 interrupt enable register P4n5INT.5 (FBH, page 0), the port 5.0 interrupt pending bit INTPND2.7 (D7H, page 0), and the port 5.0 interrupt edge selection register P4n5INT.3-.2 (FBH, page 0). The port 5.0 interrupt pending register bit lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND2.7 register at regular intervals. When the interrupt enable bit of port 5.0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND2 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND2 bit. Port 5 Control Register, High Byte (P5CONH) FDH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P5.6 P5.5 P5.4 P5.3 P5CONH bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up Figure 9-24. Port 5 Control Register, High-Byte (P5CONH) 9-19 I/O PORTS S3C94A5/F94A5 Port 5 Control Register, Low Byte (P5CONL) FEH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P5.2 P5.1 P5.0/AD15 (INT) P5CONL.6-.5 and P5CONL.4-.3 bit-pair pin configuration settings: 00 01 10 11 Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up P5CONL.2-.0 bits pin configuration settings: 000 001 010 011 100 Other Values Input mode Push-pull output mode N-channel open-drain output mode Input mode with pull-up Alternative function (AD15) Not available Figure 9-25. Port 5 Control Register, Low-Byte (P5CONL) Port 4 and 5 Interrupt Control Register (P4n5INT) FBH, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used P5.0 P4.7 (INT) (INT) P5.0 (INT) P4.7 (INT) P4n5INT.5 and P4n5INT.4 bit configuration settings: 0 1 Disable interrupt Enable interrupt P4n5INT.3-.2 and P4n5INT.1-.0 bit-pair configuration settings: 00 01 10 11 Falling edge detection Rising edge detection Both rising and falling edges detection Not available Figure 9-26. Port 4 and 5 Interrupt Control Register (P4n5INT) 9-20 S3C94A5/F94A5 I/O PORTS Interrupt Pending Register 2 (INTPND2) D7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P5.0 P4.7 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND2 bit configuration settings: 0 1 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) Figure 9-27. Interrupt Pending Register 2 (INTPND2) 9-21 S3C94A5/F94A5 BASIC TIMER 10 OVERVIEW BASIC TIMER Basic timer (BT) can be used in two different ways: -- As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. -- To signal the end of the required oscillation stabilization interval after a reset or a stop mode release. The functional components of the basic timer block are: -- Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer -- 8-bit basic timer counter, BTCNT (DDH, read-only) -- Basic timer control register, BTCON (DCH, read/write) 10-1 BASIC TIMER S3C94A5/F94A5 BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fxx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7-BTCON.4. The 8-bit basic timer counter, BTCNT (page 0, DDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to BTCON.0. Basic Timer Control Register (BTCON) DCH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Watchdog function enable bits: 1010B = Disable watchdog timer Other Value = Enable watchdog timer Divider clear bit for basic timer and timer counters: 0 = No effect 1 = Clear divider Basic timer counter clear bit: 0 = No effect 1 = Clear BTCNT Basic timer input clock selection bits: 00 = fXX/4096 01 = fXX/1024 10 = fXX/128 11 = fXX/16 Figure 10-1. Basic Timer Control Register (BTCON) 10-2 S3C94A5/F94A5 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7-BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation. In summary, the following events occur when stop mode is released: 1. 2. During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows. When a BTCNT.3 overflow occurs, normal CPU operation resumes. 3. 4. 10-3 BASIC TIMER S3C94A5/F94A5 RESET or STOP Bit 1 Bits 3, 2 Data Bus fXX/4096 fXX/1024 fXX DIV fXX/128 fXX/16 R Start the CPU (note) MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF RESET Clear Basic Timer Control Register (Write '1010xxxxB' to Disable) Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). Figure 10-2. Basic Timer Block Diagram 10-4 S3C94A5/F94A5 16-BIT TIMER 0 11 OVERVIEW -- Interval timer mode -- PWM mode 16-BIT TIMER 0 Timer/counter 0 has three operating modes, one of which you select using the appropriate T0CON setting: -- Capture input mode with a rising or falling edge trigger at the P3.4 pin Timer/counter 0 has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer -- External clock input (P3.5, T0CLK) -- 16-bit counter(T0CNTH,T0CNTL), 16-bit comparator, and 16-bit reference data register(T0DATAH,T0DATAL) -- I/O pins for capture input, match output, or PWM output (P3.4/T0CAP, P3.3/T0OUT, P3.3/T0PWM) -- Timer 0 overflow interrupt and match/capture interrupt generation -- Timer 0 control register, T0CON (page 0, B4H, read/write) TIMER/COUNTER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to -- Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) -- Select the timer 0 input clock frequency -- Clear the timer 0 counter, T0CNTH/T0CNTL -- Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt 11-1 16-BIT TIMER 0 S3C94A5/F94A5 T0CON is located in page 0, at address B4H, and is read/write addressable using register addressing mode. A reset clears T0CON to "00H". This sets timer 0 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.2. To enable the timer 0 match/capture interrupt (T0INT), you must write T0CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls INTPND3.0. When a "1" is detected, a timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit, INTPND3.0. Timer 0 Control Register (T0CON) B4H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 0 input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = External clock (P3.5/T0CLK) falling edge 110 = External clock (P3.5/T0CLK) rising edge 111 = Counter stop Timer 0 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 0 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 0 counter clear bit: 0 = No effect 1 = Clear the timer 0 counter (when write) Timer 0 operating mode selection bits: 00 = Interval mode (P3.3/T0OUT) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Figure 11-1. Timer 0 Control Register (T0CON) 11-2 S3C94A5/F94A5 16-BIT TIMER 0 Interrupt Pending Register 3 (INTPND3) D8H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 0 match/capture interrupt pending bit Watch timer interrupt pending bit Timer 0 overflow interrupt pending bit Timer 1 match/capture interrupt pending bit SIO interrupt pending bit Timer 1 overflow interrupt pending bit Timer 2 match/capture interrupt pending bit Timer 2 overflow interrupt pending bit 0 = Interrupt request is not pending, pending bit clear when write "0". 1 = Interrupt request is pending Figure 11-2. Interrupt Pending Register 3 (INTPND3) 11-3 16-BIT TIMER 0 S3C94A5/F94A5 TIMER 0 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, T0DATAH/T0DATAL. The match signal generates a timer 0 match interrupt (T0INT) and clears the counter. If, for example, you write the value "1087H" to T0DATAH/T0DATAL, the counter will increment until it reaches "1087H". At this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 11-3). Capture Signal CLK 16-Bit Up Counter R (Clear) Interrupt Enable/Disable T0CON.1 16-Bit Comparator Match M U X T0INT INTPND3.0 Pending T0OUT (P3.3) (Match INT) Timer 0 Buffer Register Match Signal T0CON.2 T0OVF Timer 0 Data Register T0CON.4-.3 Figure 11-3. Simplified Timer 0 Function Diagram: Interval Timer Mode 11-4 S3C94A5/F94A5 16-BIT TIMER 0 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM (P3.3) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H". Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T0PWM (P3.3) pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK x 65536 (see Figure 11-4). T0CON.0 T0OVF CLK 16-Bit Up Counter INTPND3.1 (Overflow INT) Capture Signal Interrupt Enable/Disable T0CON.1 Match 16-Bit Comparator M U X T0INT INTPND3.0 Pending (Match INT) T0PWM Output (P3.3) High level when data > counter, Lower level when data < counter Timer 0 Buffer Register Match Signal T0CON.2 T0OVF Timer 0 Data Register T0CON.4-.3 Figure 11-4. Simplified Timer 0 Function Diagram: PWM Mode 11-5 16-BIT TIMER 0 S3C94A5/F94A5 Capture Mode In capture mode, a signal edge that is detected at the T0CAP (P3.4) pin opens a gate and loads the current counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source: the signal edge at the T0CAP (P3.4) pin. You select the capture input by setting the values of the timer 0 capture input selection bits in the port 3 control register, P3CONH.4-.3, (page 0, F2H). When P3CONH.4-.3 is "00", the T0CAP input is selected. Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the timer 0 data register. By reading the captured data value in T0DATAH/T0DATAL, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 11-5). T0CON.0 T0OVF CLK 16-Bit Up Counter INTPND3.1 (Overflow INT) Interrupt Enable/Disable T0CON.1 M U X T0INT INTPND3.0 Pending (Capture INT) T0CAP input (P3.4) T0CON.4-.3 Match Signal T0CON.4-.3 Timer 0 Data Register Figure 11-5. Simplified Timer 0 Function Diagram: Capture Mode 11-6 S3C94A5/F94A5 16-BIT TIMER 0 T0CON.0 T0CON.7-.5 Data BUS fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 MUX T0CLK 8 16-Bit Up Counter R (Read-Only) OVF INTPND3.1 T0OVF T0CON.2 Clear T0CON.1 M U X T0INT INTPND3.0 T0OUT T0PWM T0CON.4-.3 Match signal T0CON.2 T0OVF Timer 0 Data Register 8 Data BUS 16-Bit Comparator Match M U X Timer 0 Buffer Register T0CAP T0CON.4-.3 Figure 11-6. Timer 0 Block Diagram 11-7 S3C94A5/F94A5 16-BIT TIMER 1 12 OVERVIEW -- Interval timer mode -- PWM mode 16-BIT TIMER 1 Timer/counter 1 has three operating modes, one of which you select using the appropriate T1CON setting: -- Capture input mode with a rising or falling edge trigger at the P4.2 pin Timer/counter 1 has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer -- 16-bit counter(T1CNTH,T1CNTL), 16-bit comparator, and 16-bit reference data register(T1DATAH,T1DATAL) -- I/O pins for capture input, match output, or PWM output (P4.2/T1CAP, P4.0/T1OUT, P4.0/T1PWM) -- Timer 1 overflow interrupt and match/capture interrupt generation -- Timer 1 control register, T1CON (page 0, B9H, read/write) TIMER/COUNTER 1 CONTROL REGISTER (T1CON) You use the timer 1 control register, T1CON, to -- Select the timer 1 operating mode (interval timer, capture mode, or PWM mode) -- Select the timer 1 input clock frequency -- Clear the timer 1 counter, T1CNTH/T1CNTL -- Enable the timer 1 overflow interrupt or timer 1 match/capture interrupt 12-1 16-BIT TIMER 1 S3C94A5/F94A5 T1CON is located in page 0, at address B9H, and is read/write addressable using register addressing mode. A reset clears T1CON to "00H". This sets timer 1 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 1 interrupts. You can clear the timer 1 counter at any time during normal operation by writing a "1" to T1CON.2. To enable the timer 1 match/capture interrupt (T1INT), you must write T1CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls INTPND3.2. When a "1" is detected, a timer 1 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 match/capture interrupt pending bit, INTPND3.2. Timer 1 Control Register (T1CON) B9H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 1 input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 111 = Counter stop Other Value = Not available Timer 1 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 1 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 1 counter clear bit: 0 = No effect 1 = Clear the timer 1 counter (when write) Timer 1 operating mode selection bits: 00 = Interval mode (P4.0/T1OUT) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Figure 12-1. Timer 1 Control Register (T1CON) 12-2 S3C94A5/F94A5 16-BIT TIMER 1 Interrupt Pending Register 3 (INTPND3) D8H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 0 match/capture interrupt pending bit Watch timer interrupt pending bit Timer 0 overflow interrupt pending bit Timer 1 match/capture interrupt pending bit SIO interrupt pending bit Timer 1 overflow interrupt pending bit Timer 2 match/capture interrupt pending bit Timer 2 overflow interrupt pending bit 0 = Interrupt request is not pending, pending bit clear when write "0". 1 = Interrupt request is pending Figure 12-2. Interrupt Pending Register 3 (INTPND3) 12-3 16-BIT TIMER 1 S3C94A5/F94A5 TIMER 1 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1 reference data register, T1DATAH/T1DATAL. The match signal generates a timer 1 match interrupt (T1INT) and clears the counter. If, for example, you write the value "1087H" to T1DATAH/T1DATAL, the counter will increment until it reaches "1087H". At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 1 output pin is inverted (see Figure 12-3). Capture Signal CLK 16-Bit Up Counter R (Clear) Interrupt Enable/Disable T1CON.1 16-Bit Comparator Match M U X T1INT INTPND3.2 Pending T1OUT (P4.0) (Match INT) Timer 1 Buffer Register Match Signal T1CON.2 T1OVF Timer 1 Data Register T1CON.4-.3 Figure 12-3. Simplified Timer 1 Function Diagram: Interval Timer Mode 12-4 S3C94A5/F94A5 16-BIT TIMER 1 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1PWM (P4.0) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H". Although you can use the match signal to generate a timer 1 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T1PWM (P4.0) pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK x 65536 (see Figure 12-4). T1CON.0 T1OVF CLK 16-Bit Up Counter INTPND3.3 (Overflow INT) Capture Signal Interrupt Enable/Disable T1CON.1 16-Bit Comparator Match M U X T1INT INTPND3.2 Pending (Match INT) T1PWM Output (P4.0) High level when data > counter, Lower level when data < counter Timer 1 Buffer Register Match Signal T1CON.2 T1OVF Timer 1 Data Register T1CON.4-.3 Figure 12-4. Simplified Timer 1 Function Diagram: PWM Mode 12-5 16-BIT TIMER 1 S3C94A5/F94A5 Capture Mode In capture mode, a signal edge that is detected at the T1CAP (P4.2) pin opens a gate and loads the current counter value into the timer 1 data register. You can select rising or falling edges to trigger this operation. Timer 1 also gives you capture input source: the signal edge at the T1CAP (P4.2) pin. You select the capture input by setting the values of the timer 1 capture input selection bits in the port 4 control register, P4CONM.1-.0, (page 0, F9H). When P4CONM.1-.0 is "00", the T1CAP input is selected. Both kinds of timer 1 interrupts can be used in capture mode: the timer 1 overflow interrupt is generated whenever a counter overflow occurs; the timer 1 match/capture interrupt is generated whenever the counter value is loaded into the timer 1 data register. By reading the captured data value in T1DATAH/T1DATAL, and assuming a specific value for the timer 1 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin (see Figure 12-5). T1CON.0 T1OVF CLK 16-Bit Up Counter INTPND3.3 (Overflow INT) Interrupt Enable/Disable T1CON.1 M U X T1INT INTPND3.2 Pending (Capture INT) T1CAP input (P4.2) T1CON.4-.3 Match Signal T1CON.4-.3 Timer 1 Data Register Figure 12-5. Simplified Timer 1 Function Diagram: Capture Mode 12-6 S3C94A5/F94A5 16-BIT TIMER 1 T1CON.0 T1CON.7-.5 Data BUS fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 16-Bit Comparator Match M U X Timer 1 Buffer Register T1CON.4-.3 Match signal T1CON.2 T1OVF Timer 1 Data Register 8 Data BUS M U X INTPND3.2 T1OUT T1PWM MUX 16-Bit Up Counter R (Read-Only) Clear 8 OVF INTPND3.3 T1OVF T1CON.2 T1CON.1 T1INT T1CAP T1CON.4-.3 Figure 12-6. Timer 1 Block Diagram 12-7 S3C94A5/F94A5 8-BIT TIMER 2 13 OVERVIEW -- Interval timer mode -- PWM mode 8-BIT TIMER 2 Timer/counter 2 has three operating modes, one of which you select using the appropriate T2CON setting: -- Capture input mode with a rising or falling edge trigger at the P4.3 pin Timer/counter 2 has the following functional components: -- Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer -- 8-bit counter(T2CNT), 8-bit comparator, and 8-bit reference data register(T2DATA) -- I/O pins for capture input, match output, or PWM output (P4.3/T2CAP, P4.1/T2OUT, P4.1/T2PWM) -- Timer 2 overflow interrupt and match/capture interrupt generation -- Timer 2 control register, T2CON (page 0, BEH, read/write) TIMER/COUNTER 2 CONTROL REGISTER (T2CON) You use the timer 2 control register, T2CON, to -- Select the timer 2 operating mode (interval timer, capture mode, or PWM mode) -- Select the timer 2 input clock frequency -- Clear the timer 2 counter, T2CNT -- Enable the timer 2 overflow interrupt or timer 2 match/capture interrupt 13-1 8-BIT TIMER 2 S3C94A5/F94A5 T2CON is located in page 0, at address BEH, and is read/write addressable using register addressing mode. A reset clears T2CON to "00H". This sets timer 2 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 2 interrupts. You can clear the timer 2 counter at any time during normal operation by writing a "1" to T2CON.2. To enable the timer 2 match/capture interrupt (T2INT), you must write T2CON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls INTPND3.4. When a "1" is detected, a timer 2 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 2 match/capture interrupt pending bit, INTPND3.4. Timer 2 Control Register (T2CON) BEH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 2 input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 111 = Counter stop Other Values = Not abailable Timer 2 overflow interrupt enable bit: 0 = Disable overflow interrupt 1 = Enable overflow interrupt Timer 2 match/capture interrupt enable bit: 0 = Disable interrupt 1 = Enable interrupt Timer 2 counter clear bit: 0 = No effect 1 = Clear the timer 2 counter (when write) Timer 2 operating mode selection bits: 00 = Interval mode (P4.1/T2OUT) 01 = Capture mode (capture on rising edge, counter running, OVF can occur) 10 = Capture mode (capture on falling edge, counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Figure 13-1. Timer 2 Control Register (T2CON) 13-2 S3C94A5/F94A5 8-BIT TIMER 2 Interrupt Pending Register 3 (INTPND3) D8H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Timer 0 match/capture interrupt pending bit Watch timer interrupt pending bit Timer 0 overflow interrupt pending bit Timer 1 match/capture interrupt pending bit SIO interrupt pending bit Timer 1 overflow interrupt pending bit Timer 2 match/capture interrupt pending bit Timer 2 overflow interrupt pending bit 0 = Interrupt request is not pending, pending bit clear when write "0". 1 = Interrupt request is pending Figure 13-2. Interrupt Pending Register 3 (INTPND3) 13-3 8-BIT TIMER 2 S3C94A5/F94A5 TIMER 2 FUNCTION DESCRIPTION Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 2 reference data register, T2DATA. The match signal generates a timer 2 match interrupt (T2INT) and clears the counter. If, for example, you write the value "10H" to T2DATA, the counter will increment until it reaches "10H". At this point, the timer 2 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 2 output pin is inverted (see Figure 13-3). Capture Signal CLK 8-Bit Up Counter R (Clear) Interrupt Enable/Disable T2CON.1 8-Bit Comparator Match M U X T2INT INTPND3.4 Pending T2OUT (P4.1) (Match INT) Timer 2 Buffer Register Match Signal T2CON.2 T2OVF Timer 2 Data Register T2CON.4-.3 Figure 13-3. Simplified Timer 2 Function Diagram: Interval Timer Mode 13-4 S3C94A5/F94A5 8-BIT TIMER 2 Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T2PWM (P4.1) pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 2 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a timer 2 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T2PWM (P4.1) pin is held to Low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to tCLK x 256 (see Figure 13-4). T2CON.0 T2OVF CLK 8-Bit Up Counter INTPND3.5 (Overflow INT) Capture Signal Interrupt Enable/Disable T2CON.1 Match 8-Bit Comparator M U X T2INT INTPND3.4 Pending (Match INT) T2PWM Output (P4.1) High level when data > counter, Lower level when data < counter Timer 2 Buffer Register Match Signal T2CON.2 T2OVF Timer 2 Data Register T2CON.4-.3 Figure 13-4. Simplified Timer 2 Function Diagram: PWM Mode 13-5 8-BIT TIMER 2 S3C94A5/F94A5 Capture Mode In capture mode, a signal edge that is detected at the T2CAP (P4.3) pin opens a gate and loads the current counter value into the timer 2 data register. You can select rising or falling edges to trigger this operation. Timer 2 also gives you capture input source: the signal edge at the T2CAP (P4.3) pin. You select the capture input by setting the values of the timer 2 capture input selection bits in the port 4 control register, P4CONM.3-.2, (page 0, F9H). When P4CONM.3-.2 is "00", the T2CAP input is selected. Both kinds of timer 2 interrupts can be used in capture mode: the timer 2 overflow interrupt is generated whenever a counter overflow occurs; the timer 2 match/capture interrupt is generated whenever the counter value is loaded into the timer 2 data register. By reading the captured data value in T2DATA, and assuming a specific value for the timer 2 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T2CAP pin (see Figure 13-5). T2CON.0 T2OVF CLK 8-Bit Up Counter INTPND3.5 (Overflow INT) Interrupt Enable/Disable T2CON.1 M U X T2INT INTPND3.4 Pending (Capture INT) T2CAP input (P4.3) T2CON.4-.3 Match Signal T2CON.4-.3 Timer 2 Data Register Figure 13-5. Simplified Timer 2 Function Diagram: Capture Mode 13-6 S3C94A5/F94A5 8-BIT TIMER 2 T2CON.0 T2CON.7-.5 Data BUS fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 8-Bit Comparator Match M U X Timer 2 Buffer Register T2CON.4-.3 Match signal T2CON.2 T2OVF Timer 2 Data Register 8 Data BUS M U X T2INT INTPND3.4 T2OUT T2PWM MUX 8-Bit Up Counter R (Read-Only) 8 OVF INTPND3.5 T2OVF T2CON.2 Clear T2CON.1 T2CAP T2CON.4-.3 Figure 13-6. Timer 2 Block Diagram 13-7 S3C94A5/F94A5 WATCH TIMER 14 OVERVIEW WATCH TIMER Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 to "1". The watch timer overflow interrupt pending condition (INTPND3.7) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the INTPND3.7 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (INTPND3.7) is automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer speed selection bits (WTCON.3 - .2). The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. Watch timer has the following functional components: -- Real time and watch-time measurement -- Using a main clock source -- I/O pin for buzzer output frequency generator (P3.1, BUZ) -- Timing tests in high-speed mode -- Watch timer overflow interrupt generation -- Watch timer control register, WTCON (page 0, DAH, read/write) 14-1 WATCH TIMER S3C94A5/F94A5 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer. So, if you want to use the watch timer, you must write appropriate value to WTCON. Watch Timer Control Register (WTCON) DAH, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Not used Not used Watch timer INT Enable/Disable bit: 0 = Disable watch timer INT 1 = Enable watch timer INT Watch timer Enable/Disable bit: 0 = Disable watch timer; clear frequency dividing circuits 1 = Enable watch timer Buzzer signal selection bits(fx=4.19 MHz): 00 = 0.5 kHz 01 = 1 kHz 10 = 2 kHz 11 = 4 kHz Watch timer speed selection bits(fx=4.19 MHz): 00 = Set watch timer interrupt to 1 s 01 = Set watch timer interrupt to 0.5 s 10 = Set watch timer interrupt to 0.25 s 11 = Set watch timer interrupt to 3.91 ms Figure 14-1. Watch Timer Control Register (WTCON) 14-2 S3C94A5/F94A5 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON.7 WTCON.6 WTCON.5 8 WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTCON.0 Enable/Disable MUX fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Selector Circuit INTPND3.7 WT INT Enable WTCON.6 WTINT BUZ (P3.1) fW fx/128 32.768 kHz Frequency Dividing Circuit fW/2 7 fW/2 13 fW/214 fW/215 (1 Hz) fX = Main clock (where fx = 4.19 MHz) fW = Watch timer frequency Figure 14-2. Watch Timer Circuit Diagram 14-3 S3C94A5/F94A5 A/D CONVERTER 15 OVERVIEW 10-BIT ANALOG-TO-DIGITAL CONVERTER The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the sixteen input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components: -- Analog comparator with successive approximation logic -- D/A converter logic (resistor string type) -- ADC control register (ADCON) -- Sixteen multiplexed analog data input pins (AD0-AD15) -- 10-bit A/D conversion data output register (ADDATAH/ADDATAL) -- 16-bit digital input port (Alternately, I/O port) FUNCTION DESCRIPTION To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input enable at port 2, 3, 4, or 5 the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4-.7 to select one of the sixteen analog input pins (AD0-15) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in page 0, at address D1H. The pins which are not used for ADC can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 800H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.7-.4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/ADDATAL register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0-AD15 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished. 15-1 A/D CONVERTER S3C94A5/F94A5 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bit + set-up time = 50 clocks, 50 clock x 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8) Note that A/D converter needs at least 25s for conversion time. A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address D1H in page 0. It has three functions: -- Analog input pin selection (bits 4, 5, 6 and 7) -- End-of-conversion status detection (bit 3) -- ADC clock selection (bits 2 and 1) -- A/D operation start or enable (bit 0) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0-AD15) can be selected dynamically by manipulating the ADCON.4-.7 bits. And the pins not used for analog input can be used for normal I/O function. A/D Converter Control Register (ADCON) D1H, Page0, R/W (EOC bit is read-only) MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB A/D input pin selection bits: 0000 = AD0 0001 = AD1 0010 = AD2 0011 = AD3 0100 = AD4 End-of-conversion bit: 0101 = AD5 0 = Not complete Conversion 0110 = AD6 1 = Complete Conversion 0111 = AD7 1000 = AD8 1001 = AD9 1010 = AD10 1011 = AD11 1100 = AD12 1101 = AD13 1110 = AD14 1111 = AD15 Start or enable bit: 0 = Disable operation 1 = Start operation (Automatically disable the operation after conversion completes.) Clock Selection bits: 00 = fxx/16 01 = fxx/8 10 = fxx/4 11 = fxx/1 Figure 15-1. A/D Converter Control Register (ADCON) 15-2 S3C94A5/F94A5 A/D CONVERTER A/D Converter Data Register ADDATAH/ADDATAL D2H/D3H, Page 0, Read Only MSB MSB .9 .8 .7 .6 .5 .4 .3 .1 .2 .0 LSB LSB (ADDATAH) (ADDATAL) Figure 15-2. A/D Converter Data Register (ADDATAH/ADDATAL) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD. Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 VDD. 15-3 A/D CONVERTER S3C94A5/F94A5 BLOCK DIAGRAM ADCON.2-.1 ADCON.4-7 (Select one input pin of the assigned pins) AD0-AD5 Input Pins (P2.0-P2.5) AD6-AD11 Input Pins (P3.0-P3.5) AD12-AD13 Input Pins (P4.0-P4.1) AD14-AD15 Input Pins (P4.7-P5.0) Clock Selector To ADCON.3 (EOC Flag) . . . . . . . . . M U X ADCON.0 (AD/C Enable) + ADCON.0 (AD/C Enable) Analog Comparator Successive Approximation Logic & Register 10-bit D/A Converter AVREF AVSS Conversion Result (ADDATAH/ADDATAL, D2H/D3H) P2CONH/L, P3CONH/L P4CONH/L, P5CONL (Assign Pins to ADC Input) Figure 15-3. A/D Converter Functional Block Diagram 15-4 S3C94A5/F94A5 A/D CONVERTER VDD Reference Voltage Input (AVREF VDD) AVREF + 10F C 103 VDD S3C94A5 AD0-AD15 Analog Input Pin C 101 AVSS Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy 15-5 S3C94A5/F94A5 SERIAL I/O INTERFACE 16 OVERVIEW -- Clock selector logic SERIAL I/O INTERFACE Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are: -- 8-bit control register (SIOCON) -- 8-bit data buffer (SIODATA) -- 8-bit prescaler (SIOPS) -- 3-bit serial clock counter -- Serial data I/O pins (SI, SO) -- Serial clock input/output pin (SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO module, follow these basic steps: 1. 2. 3. 4. 5. Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P4CONM and P4CONH register if necessary. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1". When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. When the shift operation (transmit/receive) is completed, the SIO pending bit (INTPND3.6) is set to "1" and SIO interrupt request is generated. 16-1 SERIAL I/O INTERFACE S3C94A5/F94A5 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module. -- Clock source selection (internal or external) for shift clock -- Interrupt enable -- Edge selection for shift operation -- Clear 3-bit counter and start shift operation -- Shift operation (transmit) enable -- Mode selection (transmit/receive or receive-only) -- Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first. Serial I/O Module Control Register (SIOCON) E1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB SIO shift clock selection bit: 0 = Internal clock (P.S Clock) 1 = External clock (SCK) Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive only mode 1 = Transmit/receive mode Not used SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting Shift clock edge selection bit: 0 = tX at falling edeges, rx at rising edges. 1 = tX at rising edeges, rx at falling edges. Figure 16-1. Serial I/O Module Control Register (SIOCON) 16-2 S3C94A5/F94A5 SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/2)/(Prescaler value + 1), or SCK input clock. SIO Pre-scaler Register (SIOPS) E3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Baud rate = (fXX/2)/(SIOPS + 1) Figure 16-2. SIO Prescaler Register (SIOPS) SIO BLOCK DIAGRAM CLK 3-Bit Counter Clear SIO INT INTPND3.6 Pending SIOCON.3 SIOCON.7 SIOCON.4 (Edge Select) SCK SIOPS (E3H, page 0) fxx 8-bit P.S. 1/2 M U X CLK 8-Bit SIO Shift Buffer (SIODATA, E2H, page 0) SIOCON.2 (Shift Enable) SIOCON.1 (Interrupt Enable) SIOCON.5 (Mode Select) SO SIOCON.6 (LSB/MSB First Mode Select) 8 SI Data Bus Figure 16-3. SIO Functional Block Diagram 16-3 SERIAL I/O INTERFACE S3C94A5/F94A5 SERIAL I/O TIMING DIAGRAM (SIO) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO INT Set SIOCON.3 Transmit Complete Figure 16-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIO INT Set SIOCON.3 Transmit Complete Figure 16-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1) 16-4 S3C94A5/F94A5 ELECTRICAL DATA 17 OVERVIEW ELECTRICAL DATA In this chapter, S3C94A5/F94A5 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: -- Absolute maximum ratings -- D.C. electrical characteristics -- Data retention supply voltage in Stop mode -- Stop mode release timing when initiated by an external interrupt -- Stop mode release timing when initiated by a Reset -- I/O capacitance -- A.C. electrical characteristics -- A/D converter electrical characteristics -- Input timing for external interrupt -- Input timing for RESET -- Serial data transfer timing -- Oscillation characteristics -- Oscillation stabilization time -- Operating voltage range 17-1 ELECTRICAL DATA S3C94A5/F94A5 Table 17-1. Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Output voltage Output current High Symbol VDD VI VO IOH Ports 1-5 - One I/O pin active All I/O pins active 42-SDIP 44-QFP Output current Low IOL One I/O pin active All I/O pin active 42-SDIP 44-QFP Operating temperature Storage temperature TA TSTG - - + 30 + 100 + 150 C C Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 60 - 90 Unit V V V mA mA - 25 to + 85 - 65 to + 150 17-2 S3C94A5/F94A5 ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Operating voltage Symbol VDD Conditions fx = 0.4-4MHz fx = 0.4-8MHz fx = 0.4-12 MHz Input high voltage VIH1 VIH2 VIH3 Input low voltage VIL1 VIL2 VIL3 Output high voltage VOH VOL1 VOL2 Input high leakage current ILIH1 ILIH2 Ports 2, 5 Ports 1, 3, 4 nRESET XIN, XOUT Ports 2, 5 Ports 1, 3, 4, nRESET XIN, XOUT VDD = 2.7 to 5.5 V; All output ports; IOH = -3 mA Output low voltage VDD = 2.7 to 5.5 V; All output ports; IOL = 15 mA VDD = 3.3 V; All output ports; IOL = 20 mA VI = VDD; All input pins except XIN, XOUT VI = VDD; XIN, XOUT - - 20 - - 3 A - - 1.0 - - 1.0 V Min 2.0 2.7 3.0 0.7 VDD 0.8 VDD VDD - 0.1 - - - VDD - 1.0 Typ - - - - - - - - - - Max 5.5 5.5 5.5 VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 VDD V V V Unit V 17-3 ELECTRICAL DATA S3C94A5/F94A5 Table 17-2. D.C. Electrical Characteristics (Continued) (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Input low leakage current Symbol ILIL1 Conditions VI = 0 V; All input pins except nRESET, ILIL2 VI = 0 V; XIN, XOUT VO = VDD All output pins VO = 0 V All output pins RL1 VI = 0 V; VDD = 5V, TA = 25C Ports 1-5 VDD = 3V, TA = 25C RL2 VI = 0 V; VDD = 5V, TA = 25C nRESET VDD = 3V, TA = 25C Oscillator feed back resistors NOTE: Min - Typ - Max -3 Unit A ILIL2 Output high leakage current Output low leakage current Pull-up resistor ILOH ILOL -20 - - 15 - - 35 3 -3 70 k 30 150 70 250 140 400 300 300 500 600 700 1500 k ROSC1 VDD = 5 V, TA = 25 C XIN = VDD, XOUT = 0V Low leakage current is absolute value. 17-4 S3C94A5/F94A5 ELECTRICAL DATA Table 17-2. D.C. Electrical Characteristics (Concluded) (TA = - 25C to + 85C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Conditions Run mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% 12.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz IDD2 Idle mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% 12.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz IDD3(2) Stop mode; VDD = 5 V 10%, TA = 25 C Stop mode; VDD = 3 V 10%, TA = 25 C TA = -25 C to + 85 C NOTES: 1. Supply current does not include current drawn through internal pull-up resistors and ADC. 2. IDD3 is current when main clock and oscillation stops. 3. Every values in this table is measured when bits 4 -3 of the system clock control register (CLKCON.4-.3) is set to 11B. Min - Typ 6.0 2.5 2.5 1.5 1.5 1.0 0.5 0.4 0.5 Max 18.0 6.0 5.0 3.0 4.0 2.0 1.6 0.8 3 Unit mA A 0.3 2 - 10 17-5 ELECTRICAL DATA S3C94A5/F94A5 Table 17-3. Data Retention Supply Voltage in Stop Mode (TA = - 25 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions - Stop mode, TA = 25 C VDDDR = 2.0 V Min 2.0 - Typ - - Max 5.5 1 Unit V A Idle Mode (Basic Timer Active) ~ ~ ~ ~ Stop Mode Data Retention Mode Normal Operating Mode VDD VDDDR Execution of STOP Instruction 0.8 VDD tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock. Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt 17-6 S3C94A5/F94A5 ELECTRICAL DATA RESET Occurs Oscillation Stabilization TIme Normal Operating Mode ~ ~ ~ ~ Stop Mode Data Retention Mode VDD VDDDR Execution of STOP Instrction nRESET 0.2 VDD 0.8 VDD tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock. Figure 17-2. Stop Mode Release Timing When Initiated by a RESET Table 17-4. Input/Output Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO Conditions f = 1 MHz; unmeasured pins are connected to VSS Min - Typ - Max 10 Unit pF 17-7 ELECTRICAL DATA S3C94A5/F94A5 Table 17-5. A.C. Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.7 V to 5.5 V) Parameter SCK cycle time Symbol tKCY Conditions External SCK source Internal SCK source SCK high, low width tKH, tKL External SCK source Internal SCK source SI setup time to SCK high SI hold time to SCK high tSIK External SCK source Internal SCK source tKSI External SCK source Internal SCK source Output delay for SCK to SO Interrupt input, High, Low width nRESET input Low width tKSO External SCK source Internal SCK source tINTH, tINTL tRSL All interrupt VDD = 3 V Input VDD = 3 V 500 700 Min 330 330 165 tKCY /2-20 80 80 130 130 - - 100 80 - ns s ns Typ - Max - Unit ns 10 - - 17-8 S3C94A5/F94A5 ELECTRICAL DATA Table 17-6. A/D Converter Electrical Characteristics (TA = - 25C to + 85C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Resolution Total accuracy Integral linearity error Differential linearity error Offset error of top Offset error of bottom Conversion time (1) Analog input voltage Analog input impedance Analog reference voltage Analog ground Analog input current Analog block current (2) Symbol - - ILE DLE EOT EOB TCON VIAN RAN AVREF AVSS IADIN IADC 10-bit resolution 50 x fxx/4, fxx = 8MHz - - - - AVREF = VDD = 5 V AVREF = VDD = 5 V AVREF = VDD = 3 V AVREF = VDD = 5 V When power down mode Conditions - VDD = 5.12 V AVREF = 5.12 V AVSS = 0 V CPU clock = 8 MHz Min - - - - - - 25 AVSS 2 2.7 VSS - - Typ 10 - - - 1 1 - - 1000 - - - 1 0.5 100 Max - 3 2 1 3 3 - AVREF - VDD VSS+0.3 10 3 1.5 500 nA S V M V V A mA Unit bit LSB NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. IADC is an operating current during A/D conversion. tINTL tINTH External Interrupt 0.8 VDD 0.2 VDD NOTE: The unit tCPU means one CPU clock period. Figure 17-3. Input Timing for External Interrupts 17-9 ELECTRICAL DATA S3C94A5/F94A5 tRSL nRESET 0.2 VDD Figure 17-4. Input Timing for nRESET tKCY tKL SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO tKH SO Output Data Figure 17-5. Serial Data Transfer Timing 17-10 S3C94A5/F94A5 ELECTRICAL DATA Table 17-7. Main Oscillation Characteristics (TA = - 25C to + 85C) Oscillator Crystal Clock Configuration C1 XIN Parameter Crystal oscillation frequency Test Condition 3.0 V - 5.5 V 2.7 V - 5.5 V 2.0 V - 5.5 V Min 0.4 0.4 0.4 Typ - - - Max 12 8 4 Units MHz XOUT C2 Ceramic Oscillator C1 XIN Ceramic oscillation frequency 3.0 V - 5.5 V 2.7 V - 5.5 V 2.0 V - 5.5 V 0.4 0.4 0.4 - - - 12 8 4 XOUT C2 External Clock XIN input frequency XIN 3.0 V - 5.5 V 2.7 V - 5.5 V 2.0 V - 5.5 V 0.4 0.4 0.4 - - - 12 8 4 XOUT RC Oscillator (mode1) Frequency XIN R XOUT 5.0 V 3.0 V 0.4 0.4 - - 2 1 MHz 17-11 ELECTRICAL DATA S3C94A5/F94A5 Table 17-8. Main Oscillator Stabilization Time (TA = - 25 C to + 85 C, VDD = 2.0 V to 3.6 V) Oscillator Crystal Ceramic fx > 1 MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. External clock XIN input high and low width (t XH, tXL) 41 - 1250 ns Test Condition Min - - Typ - - Max 40 10 Unit ms ms 1/fx tXL tXH XIN VDD-0.1 V 0.1 V Figure 17-6. Clock Timing Measurement at XIN 17-12 S3C94A5/F94A5 ELECTRICAL DATA Table 17-9. External RC Oscillation (Mode 2) Characteristics (TA = - 25 C to + 85 C, VDD = 2.7 V to 5.5 V) Parameter RC oscillator frequency range (1) Accuracy of RC oscillation (2) Symbol fERC ACCERC Conditions TA = 25 C VDD = 3.3 V, TA = 25 C VDD = 3.3 V, TA = -25 C to 85 C Min 4 -7 -15 Typ - - - Max 8 +7 +15 Unit MHz % RC oscillator setup time (3) tSUERC TA = 25 C - - 10 ms NOTES: 1. The frequency is adjusted by external resistor. 2. The min/max frequencies are within the range of RC OSC frequency (4 MHz to 8 MHz). 3. Data based on characterization results, not tested in production. 4. The external resistor is connected between VDD and XIN pin (XOUT pin should be open). Table 17-10. Internal RC Oscillation Characteristics (TA = - 10 C to + 70 C, VDD = 3.0 V to 5.5 V) Parameter RC oscillator frequency range (1) Symbol fIRC Conditions VDD = 3.3 V, TA = 25 C VDD = 3.3 V, TA = -10 C to 70 C Clock duty ratio RC oscillator setup time (2) TOD tSUIRC TA = 25 C - 40 - 50 - 60 10 % ms Min 7 6 Typ 9 9 Max 11 12 Unit MHz MHz NOTES: 1. The internal RC OSC frequency is 9 MHz(typ) only. 2. Data based on characterization results, not tested in production. 3. XIN and XOUT pins should be open. 17-13 ELECTRICAL DATA S3C94A5/F94A5 Instruction Clock 3 MHz fx (oscillation frequency) 12 MHz 2 MHz 8 MHz 1 MHz 4 MHz 6.25 kHz 1 2 3 2.7 4 5 5.5 6 7 400 kHz Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 17-7. Operating Voltage Range 17-14 S3C94A5/F94A5 MECHANICAL DATA 18 OVERVIEW #42 14.00 0.2 MECHANICAL DATA The S3C94A5/F94A5 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. #22 0-15 #1 #21 39.50 MAX 39.10 0.2 0.50 (1.77) 1.00 0.1 0.1 1.78 NOTE: Dimensions are in millimeters. Figure 18-1. 42-SDIP-600 Package Dimensions 0.51 MIN 3.30 0.3 5.08 MAX 3.50 0.2 0.2 5 18-1 +0 - 0. .1 05 42-SDIP-600 15.24 MECHANICAL DATA S3C94A5/F94A5 13.20 0.3 0-8 10.00 0.2 + 0.10 0.15 - 0.05 13.20 0.3 10.00 0.2 44-QFP-1010B 0.80 0.20 #1 0.80 + 0.10 0.10 MAX #44 0.35 - 0.05 (1.00) 0.05 MIN 2.05 0.10 2.30 MAX NOTE : Dimensions are in millimeters. Figure 18-2. 44-QFP-1010B Package Dimensions 18-2 S3C94A5/F94A5 S3F94A5 FLASH MCU 19 OVERVIEW S3F94A5 FLASH MCU The S3F94A5 single-chip CMOS microcontroller is the Flash MCU version of the S3C94A5 microcontroller. It has an on-chip Flash MCU ROM instead of a masked ROM. The Flash ROM is accessed by serial data format. The S3F94A5 is fully compatible with the S3C94A5, both in function and in pin configuration. Because of its simple programming requirements, the S3F94A5 is ideal as an evaluation chip for the S3C94A5. 19-1 S3F94A5 FLASH MCU S3C94A5/F94A5 P1.1/INT P1.2/INT P1.3/INT P1.4/INT P1.5/INT P1.6/INT P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 P1.0/INT VDD1/VDD XIN XOUT VSS1/VSS nRESET/nRESET TEST/VPP P5.6 P5.5 P5.4 P5.3 S3F94A5 (44-QFP-1010B) P5.2 P5.1 P5.0/AD15/INT P4.7/AD14/INT P4.6/SCK/SCLK P4.5/SI P4.4/SO/SDAT P4.3/T2CAP P4.2/T1CAP P4.1/AD13/T2OUT/T2PWM P4.0/AD12/T1OUT/T1PWM Figure 19-1. S3F94A5 Pin Assignments (44-QFP-1010B) 19-2 P2.5/AD5 AVREF AVSS P3.0/AD6/CLO/INT P3.1/AD7/BUZ/INT P3.2/AD8/INT P3.3/AD9/T0OUT/T0PWM/INT P3.4/AD10/T0CAP/INT P3.5/AD11/T0CLK/INT VDD2 VSS2 12 13 14 15 16 17 18 19 20 21 22 S3C94A5/F94A5 S3F94A5 FLASH MCU P1.6/INT P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5 AVREF AVSS P3.0/AD6/CLO/INT P3.1/AD7/BUZ/INT P3.2/AD8/INT P3.3/AD9/T0OUT/T0PWM.INT P3.4/AD10/T0CAP/INT P3.5/AD11/T0CLK/INT P4.0/AD12/T1OUT/T1PWM P4.1/AD13/T2OUT/T2PWM P4.2/T1CAP P4.3/T2CAP SDAT/P4.4/SO P4.5/SI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P1.5/INT P1.4/INT P1.3/INT P1.2/INT P1.1/INT P1.0/INT VDD1/VDD XIN XOUT VSS1/VSS nRESET/nRESET TEST/VPP P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0/AD15/INT P4.7/AD14/INT P4.6/SCK/SCLK Figure 19-2. S3F94A5 Pin Assignments (42-SDIP-600) (42-SDIP-600) S3F94A5 19-3 S3F94A5 FLASH MCU S3C94A5/F94A5 Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip Pin Name P4.4 Pin Name SDAT Pin No. 27(20) During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for flash ROM cell writing (indicates that flash MCU enters into the writing mode). When 12.5 V is applied, flash MCU is in writing mode and when 5 V is applied, flash MCU is in reading mode. (option) Chip Initialization Logic power supply pin. VDD should be tied to +5 V during programming. NOTE: Parentheses indicate pin number for 42-SDIP-600 package. P4.6 TEST SCLK VPP 29(22) 38(31) I/O I nRESET VDD1/VSS1 nRESET VDD/VSS 39(32) 43(36)/40(33) I - Table 19-2. Comparison of S3F94A5 and S3C94A5 Features Characteristic Program memory Operating voltage (V DD) FLASH MCU programming mode Programmability S3F94A5 16K-byte flash ROM 2.0 V to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V User program multi time S3C94A5 16K-byte mask ROM 2.0 V to 5.5 V - Programmed at the factory 19-4 S3C94A5/F94A5 S3F94A5 FLASH MCU OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP (TEST) pin of the S3F94A5, the Flash ROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 19-3 below. Table 19-3. Operating Mode Selection Criteria VDD 5V VPP(TEST) 5V 12.5 V 12.5 V 12.5 V NOTE: REG/nMEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 Flash ROM read Mode Flash ROM program Flash ROM verify Flash ROM read protection "0" means Low level; "1" means High level. 19-5 S3F94A5 FLASH MCU S3C94A5/F94A5 Table 19-4. D.C. Electrical Characteristics (TA = -25 C to + 85 C, VDD = 2.0 V to 5.5 V) Parameter Supply current (1) Symbol IDD1 Run mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% Conditions 12.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz IDD2 Idle mode: VDD = 5 V 10% Crystal oscillator C1 = C2 = 22pF VDD = 3 V 10% Stop mode; VDD = 5 V 10% TA = 25C Stop mode; VDD = 5 V 10% TA = 25C TA = -25C to + 85C NOTES: 1. Supply current does not include current drawn through internal pull-up resistors and ADC. 2. IDD3 is current when main clock oscillation stops. 3. Every values in this table is measured when bits 4 -3 of the system clock control register (CLKCON.4-.3) is set to 11B. Min - Typ 6.0 2.5 2.5 1.5 1.5 1.0 0.5 0.4 0.5 Max 18.0 6.0 5.0 3.0 4.0 2.0 1.6 0.8 3 Unit mA 12.0 MHz 4.19 MHz 8.0 MHz 4.19 MHz IDD3(2) A 0.3 2 - 10 19-6 S3C94A5/F94A5 S3F94A5 FLASH MCU Instruction Clock 3 MHz fx (oscillation frequency) 12 MHz 2 MHz 8 MHz 1 MHz 4 MHz 6.25 kHz 1 2 3 2.7 4 5 5.5 6 7 400 kHz Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 19-3. Operating Voltage Range 19-7 S3C94A5/F94A5 DEVELOPMENT TOOLS 20 OVERVIEW SHINE DEVELOPMENT TOOLS Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options. Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely. SAMA ASSEMBLER The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information. SASM86 The SASM86 is an relocatable assembler for Samsung's S3C9-series microcontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory. HEX2ROM HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value "FF" is filled into the unused ROM area up to the maximum ROM size of the target device automatically. TARGET BOARDS Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board. 20-1 DEVELOPMENT TOOLS S3C94A5/F94A5 IBM-PC AT or Compatible RS-232C SMDS2+ PROM/OTP Writer Unit Target Application System RAM Break/Display Unit Probe Adapter BUS Trace/Timer Unit SAM8 Base Unit POD TB94A5 Target Board EVA Chip Power Supply Unit Figure 20-1. SMDS Product Configuration (SMDS2+) 20-2 S3C94A5/F94A5 DEVELOPMENT TOOLS TB94A5 TARGET BOARD The TB94A5 target board is used for the S3C94A5 microcontroller. It is supported by the SMDS2+ development system. To User_VCC OFF RESET B1 TB94A5 IDLE STOP + + R1 D1 C1 U2 R7 R8 Smart Option SW1 AR1 C8 + C7 REV.1 '2004.06.14 ON B2 R5 R4 25 20 40 30 20 10 1 J101 42SDIP 160 J102 44QFP 1 44 1 42 40 CN1 10 50 60 70 150 160 QFP S3E94A0 EVA Chip 140 130 5 35 10 30 5 GND 40 10 35 15 25 30 20 25 23 22 22 B3 80 90 100 110 120 15 1 51 76 26 R11 R12 C14 EXTTRG1 EXTTRG2 R9 R10 C11 C12 21 SMDS2 SMDS2+ Figure 20-2. TB94A5 Target Board Configuration VCC 20-3 DEVELOPMENT TOOLS S3C94A5/F94A5 Table 20-1. Power Selection Settings for TB94A5 "To User_V CC" Settings To User_VCC Off On TB94A5 VCC VSS VCC SMDS2/SMDS2+ Target System Operating Mode Comments The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system. To User_VCC Off On TB94A5 External VCC VSS Target System The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply. VCC SMDS2/SMDS2+ NOTE: The following symbol in the "To User_VCC" Setting column indicates the electrical short (off) configuration: Table 20-2. Smart Option Switch Settings for TB94A5 "Smart Opting" Settings Smart Option ON: "0" OFF: "1" 003FH.2 003FH.1 003FH.0 Comments The Smart Option is selected by this switch. For example the main oscillator is selected as internal RC oscillation if the switch 003FH.2/003FH.1/003FH.0 is set like this "ON/ON/OFF(001b)", respectively. Refer to the Smart Option of Chapter 2. Address Spaces. 20-4 S3C94A5/F94A5 DEVELOPMENT TOOLS SMDS2+ SELECTION (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 20-3. The SMDS2+ Tool Selection Setting Setting SMDS2 SMDS2+ R/W SMDS2+ R/W Target Board Operating Mode Table 20-4. Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part External Triggers Ch1 Ch2 Comments Connector from External Trigger Sources of the Application System You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions. IDLE LED The Yellow LED is ON when the evaluation chip (S3E94A0) is in idle mode. STOP LED The Red LED is ON when the evaluation chip (S3E94A0) is in stop mode. 20-5 DEVELOPMENT TOOLS S3C94A5/F94A5 J101 42-SDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 45 46 47 J102 44-QFP 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 50 49 48 P1.6 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 AVREF VSS P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 NC NC NC NC P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 USER_VCC NC NC VSS DEMO_RSTB VSS P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 NC NC NC NC P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 AVREF VSS P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 USER_VCC VSS NC NC NC P1.0 USER_VCC NC NC VSS DEMO_RSTB VSS P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 NC NC NC Figure 20-3. Connectors (J101, J102) for TB94A5 20-6 S3C94A5/F94A5 DEVELOPMENT TOOLS Target Board J101 50-Pin DIP Connector 50-Pin Connector Target System J101 1 Target Cable for Connector Part Name: AP42SD Order Code: SM6538 42 1 42 21 22 21 22 Figure 20-4. S3C94A5 Probe Adapter for 42-SDIP Package Target Board J102 1 44 Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6305 22 23 Target System J102 1 44 50-Pin Connector 22 23 Figure 20-5. S3C94A5 Probe Adapter for 44-QFP Package 20-7 S3C9 Series Mask ROM Order Form Product description: Device Number: S3C9__________-_________ (write down the ROM code number) Product Order Form: __________ Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line) Package Pellet Wafer Package Type: SEC @ YWW Device Name @ YWW Device Name @ YWW @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly Delivery Dates and Quantities: Deliverable ROM code Customer sample Risk order Please answer the following questions: See Risk Order Sheet Required Delivery Date - Quantity Not applicable Comments See ROM Selection Form F For what kind of product will you be using this order? New product Replacement of an existing product ( Upgrade of an existing product Other ) If you are replacing an existing product, please indicate the former product name F What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation Mask Charge (US$ / Won): Customer Information: Company Name: Signatures: ____________________________ ___________________ ________________________ (Person placing the order) Telephone number _________________________ __________________________________ (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3C9 Series Request for Production at Customer Risk Customer Information: Company Name: Department: Telephone Number: Date: Risk Order Information: Device Number: Package: Intended Application: Product Model Number: S3C9________-________ (write down the ROM code number) Number of Pins: ____________ Package Type: _____________________ ________________________________________________________________ ________________________________________________________________ __________________________ __________________________ Fax: _____________________________ ________________________________________________________________ ________________________________________________________________ Customer Risk Order Agreement: We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. Order Quantity and Delivery Schedule: Risk Order Quantity: Delivery Schedule: Delivery Date (s) Quantity Comments _____________________ PCS Signatures: _______________________________ (Person Placing the Risk Order) _______________________________________ (SEC Sales Representative) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3F9 Series MTP Factory Writing Order Form (1/2) Product Description: Device Number: S3F9________-________ (write down the ROM code number) Package Pellet Package Type: Wafer _____________________ Product Order Form: If the product order form is package: Package Marking (Check One): Standard Custom A (Max 10 chars) Custom B (Max 10 chars each line) SEC @ YWW Device Name @ YWW Device Name @ YWW @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly Delivery Dates and Quantity: ROM Code Release Date Required Delivery Date of Device Quantity Please answer the following questions: F What is the purpose of this order? New product development Replacement of an existing microcontroller Upgrade of an existing product Other If you are replacing an existing microcontroller, please indicate the former microcontroller name ( ) F What are the main reasons you decided to use a Samsung microcontroller in your product? Please check all that apply. Price Development system Used same micom before Product quality Technical support Quality of documentation Features and functions Delivery on time Samsung reputation Customer Information: Company Name: Signatures: ___________________ ________________________ (Person placing the order) Telephone number _________________________ __________________________________ (Technical Manager) (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) S3F94A5 MTP Factory Writing Order Form (2/2) Device Number: S3F_________-________ (write down the ROM code number) Customer Checksums: _______________________________________________________________ Company Name: ________________________________________________________________ Signature (Engineer): ________________________________________________________________ Read Protection (1): Yes No Please answer the following questions: F Are you going to continue ordering this device? Yes If so, how much will you be ordering? No _________________ PCS F Application (Product Model ID: _______________________) Audio LCD Databank Industrials Remocon Video Caller ID Home Appliance Battery Charger Telecom LCD Game Office Automation Other Please describe in detail its application __________________________________________________________________________ NOTES: 1. Once you choose a read protection, you cannot read again the programming code from the EPROM. 2. OTP Writing will be executed in our manufacturing site. 3. The writing program is completely verified by a customer. Samsung does not take on any responsibility for errors occurred from the writing program. (For duplicate copies of this form, and for additional ordering information, please contact your local Samsung sales representative. Samsung sales offices are listed on the back cover of this book.) |
Price & Availability of S3F94A5
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |